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What CMOS 2.0 means
In the CMOS 2.0 concept, an SoC is divided into heterogeneous functional tiers. Each tier could use a technology option selected for its job and constraints, and dense three-dimensional interconnect would reconnect the tiers. Imec describes this as bringing heterogeneity inside the SoC itself, with system-technology co-optimization (STCO) guiding the allocation of functions.
That changes where scaling effort is applied. Rather than expecting every function to benefit from the same transistor-scaling path, designers could place different functions on tiers suited to their needs. One example described by imec is splitting logic between a high-drive layer and a high-density layer. The goal is to optimize the system as a whole, not to claim that a particular tier arrangement is already the best choice for every chip.
Imec fellow and 3D system integration program director Zsolt Tokei described the concept to EE Times as “disaggregating the system,” but “not necessarily in the traditional way.” The distinction is that CMOS 2.0 could change not only where complete blocks sit, but how the circuits making up those blocks are implemented.
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How it differs from chiplets and other forms of partitioning
“Beyond chiplets” does not mean chiplets are obsolete. It describes a deeper possible level of partitioning, from separating dies to distributing functions—and, at the most ambitious end, circuit elements—across tiers. The greater the partitioning, the more the design depends on dense vertical connections and coordinated design across layers.
| Approach | What is partitioned | Interconnect and distance | Maturity and main trade-off |
|---|---|---|---|
| Conventional chiplet partitioning | Finished dies or defined functional blocks; for example, a cache separated from a main die. | Communication crosses between packaged dies. The particular density and distance depend on the implementation. | An established form of heterogeneous integration, but packaging and communication remain part of the system design. |
| CMOS 2.0 functional tiers | Functions within an SoC are assigned to different technology tiers. | Dense 3D interconnect is intended to reconnect tiers and bring functions closer vertically. | A roadmap direction, not a commercial manufacturing flow; integration and design challenges remain. |
| CMOS 2.0 circuits across layers | Potentially, parts of a circuit rather than a complete block or function. | Would require very dense, reliable connections between layers. | A described future possibility, not a demonstrated product architecture; design, verification, alignment, and yield are significant challenges. |
The most speculative example comes from Tokei’s description of N-type and P-type devices potentially being completed across two layers rather than on one. That possibility illustrates how far CMOS 2.0 could go beyond placing complete blocks on separate tiers; it should not be read as a production-ready architecture.
Why move functions closer together?
The motivation is system-level data movement, especially in AI hardware, where processors, accelerators, and memory need to exchange large amounts of information. Scaling a package outward can increase communication distance and complicate power delivery, thermal management, and latency. CMOS 2.0’s ambition is to increase vertical-connection density and bring functions closer, potentially changing the balance between computation, memory, and communication.
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That is a design goal, not a measured result for a commercial CMOS 2.0 system. The cited reporting does not establish product-level bandwidth gains or energy savings. The value of a proposed arrangement would depend on its application and on whether the benefits of closer, denser connections outweigh integration and design costs.
Arm executive vice president Mohamed Awad framed the broader issue as a move from chip-centric to system-centric scaling: sustained AI performance per watt and per rack matters alongside peak performance. In that view, CPUs, accelerators, memory, interconnect, power, packaging, and software have to work together within power and thermal limits. This is Awad’s industry perspective in the EE Times interview, not an independent benchmark of CMOS 2.0.
What the latest bonding result demonstrates—and what it does not
Dense tier connections are one of the concept’s key enablers. In a May 28, 2026 press release, imec and EV Group reported wafer-to-wafer hybrid bonding on a research test vehicle with a 200 nm copper interconnect pad pitch. They also reported Cu pad-to-pad post-bond overlay below 40 nm for 100% of dies across a 300 mm wafer.
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The reported test vehicle used a routable four-layer structure, preprocessed on each wafer. The result is evidence of progress in wafer bonding and alignment under the stated test conditions. It does not establish that every wafer or commercial production run will achieve the same result, nor that a CMOS 2.0 system has been manufactured.
Imec’s technical article on front- and backside wafer connectivity describes earlier progress toward a 250 nm bonding pitch and 120 nm backside through-dielectric vias at VLSI 2025. It presents hybrid wafer bonding and backside technologies as foundational options for connecting multiple stacked tiers. These demonstrations support the roadmap, but they do not show that all the integration requirements for a working CMOS 2.0 product are solved.
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At very high connection densities, a design needs reliable connections and precise alignment across layers. Tokei put the reliability requirement bluntly: “No connection can fail.” Manufacturing may also require steps such as multi-tier bonding, wafer reconstruction, wafer flipping, debonding, and edge control. Changes to a process flow introduce integration work, while a circuit spread across layers creates new demands for design and verification.
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- Alignment and yield: More and denser connections increase the consequences of alignment errors or failed bonds. The 2026 overlay result is a test-vehicle measurement, not proof of production yield for a CMOS 2.0 system.
- Process integration: Combining tiers can require additional or modified manufacturing steps, with their own process-control and compatibility constraints.
- Design and verification: If a circuit spans layers, teams must design and verify its behavior across those layers rather than treating each layer as an independent, complete block.
- Connection density: Tokei discussed a possible future need for tens of millions of vertical connections per square millimeter. This is a future-density discussion, not a measured current capability.
Tokei also cautioned that current differences between wafer-to-wafer and die-to-wafer bonding reflect the complexity of today’s flows and the maturity of available tools; they do not necessarily define a permanent limit of the bonding mechanism. That leaves room for process development without removing the present integration challenges.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.When might CMOS 2.0 arrive?
EE Times reported Tokei’s expectation that design infrastructure and tools could take five years to develop, with first implementations ten years out. These are forecasts made in the June 17, 2026 report, not guaranteed industry milestones or announced product dates. The same report characterizes CMOS 2.0 as a roadmap rather than a commercial manufacturing flow.
The practical takeaway is to distinguish progress on individual enablers from readiness of the full approach. The 2026 hybrid-bonding result advances one important capability; it does not confirm that the design tools, process integration, yield, and verification needed for commercial systems are in place.
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What CMOS 2.0 could change for chip design
If the roadmap matures, system architects may have more ways to assign logic and other functions to tiers based on their needs, and to shorten selected communication paths through vertical integration. But the design problem would also expand: architecture, manufacturing, packaging, power, thermal behavior, and verification would need to be considered together. As Tokei put it, the approach requires teams to “re-architect from the ground up.”
For now, CMOS 2.0 is best understood as an exploration of how scaling could extend beyond conventional transistor shrink and chiplet partitioning. Its defining proposition is that the system—and potentially the circuits within it—can be repartitioned across tightly connected layers. Whether that becomes worthwhile in a given application depends on manufacturing maturity and system-level trade-offs that the available demonstrations do not yet settle.
Quick Recap
Sources
- Pat Brans, “Beyond Chiplets, CMOS 2.0 Moves Scaling into the Circuit,” EE Times, June 17, 2026. Interview reporting with Zsolt Tokei and Mohamed Awad.
- imec, “A path to high-density front- and backside wafer connectivity,” technical article, published approximately 2025.
- imec, “Imec and EV Group demonstrate wafer-to-wafer hybrid bonding with 200nm interconnect pitch and record high overlay accuracy,” press release, May 28, 2026.
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