Chinese memory maker ChangXin Memory Technologies (CXMT) says its fifth-generation DRAM platform, G5, entered mass production on September 20, 2026. The company also announced two G5-based 24Gb LPDDR5X chips for smartphones and portable electronics. The figures and production status are CXMT’s claims; the announcement does not establish production volume, customer shipments, or independently tested performance.
What CXMT announced
CXMT made the announcement at the World Manufacturing Convention in Hefei, China. It described G5 as its fifth-generation DRAM technology platform and said the platform was officially in mass production. Its announcement also introduced two G5-based LPDDR5X products, each with a capacity of 24 gigabits per die. CXMT’s announcement identifies smartphones and portable consumer electronics as the intended application areas.
DRAM is working memory that devices use to run programs and apps. CXMT says its business designs and manufactures memory for phones, PCs, tablets, servers, and other applications. Its announcement concerns components for device makers, not a consumer memory kit or a named retail product.
What CXMT says is new about the G5 process
CXMT reports three physical characteristics for G5. These are company-reported process measurements, not an independently verified ranking or a standardized process-node label.
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- 11.95 nm active-area half-pitch: CXMT says it achieved this memory-array dimension using self-aligned quadruple patterning (SAQP).
- 45:1 array-capacitor aspect ratio: The company reports this ratio for the capacitors in the array.
- 6,762 nm core-cell-array height: CXMT attributes this figure to a DRAM-optimized high-k metal gate process.
The company also describes interface engineering, saddle-fin structures, low-k spacer bitlines, and a digital-twin R&D platform that covers design, tape-out, manufacturing, and yield maintenance. Those descriptions likewise come from CXMT; the announcement does not provide independent measurements of their effects.
The 11.95 nm half-pitch should not be read as proof that G5 is a “12nm node.” A physical array dimension is not, by itself, a universal process-node designation, and the available reporting does not provide like-for-like measurements for competing DRAM processes.
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What the 50% dies-per-wafer claim means
CXMT says G5 produces at least 50% more gross dies per wafer than its fourth-generation platform, with the comparison normalized to an 8Gb density baseline. Gross dies per wafer (DPW) refers to the number of dies on a wafer before defective ones are excluded. It is not a claim that the number of usable chips, or manufacturing yield, increased by 50%. Reuters reporting republished by The Business Times also distinguishes gross dies from units remaining after defective dies are removed.
The announcement does not state how many G5 wafers CXMT is producing, the share of dies that pass final testing, or actual output. The DPW comparison therefore describes a claimed manufacturing-efficiency measure, not total supply entering the market.
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The two announced G5 LPDDR5X products
CXMT disclosed two package formats. It says both products are in mass production and intended for smartphones and portable consumer electronics; it did not identify a performance difference between them.
| Product | Capacity per die | Package format | Stated application | Status per CXMT |
|---|---|---|---|---|
| G5 LPDDR5X | 24Gb | 496-ball | Smartphones and portable consumer electronics | Mass production |
| G5 LPDDR5X | 24Gb | 245-ball | Smartphones and portable consumer electronics | Mass production |
The package options are components for product designers and manufacturers, not evidence of consumer-upgrade modules. CXMT has not named handset customers, devices using these chips, or retail SKUs.
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What the announcement does—and does not—show about competition
Reuters, in its report republished by The Business Times, describes Samsung Electronics, SK Hynix, and Micron Technology as established global DRAM competitors and frames CXMT’s announcement as an effort to strengthen a Chinese supplier. At the convention, CXMT vice-president and marketing-centre head Luo Xiaodong said: “Our process capability is now on par with the most advanced mass-produced nodes out there in the industry.” That is Luo’s characterization of CXMT’s capabilities, not an independent comparative finding.
The announcement establishes that CXMT says G5 has entered mass production and gives the company’s process figures and two product configurations. It does not provide independent benchmark results, named customer deployments, customer shipment data, or disclosed production volumes. Without those details, it cannot establish how G5 compares in measured performance or how much additional memory supply it will contribute.
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How G5 relates to CXMT’s earlier LPDDR5X announcement
CXMT’s October 28, 2025 LPDDR5X portfolio announcement described products at several capacities and data rates, but it did not say those products were built on G5. Keep that earlier portfolio separate from the G5 lineup announced in 2026.
| Announcement | Items described | Manufacturing or availability status stated |
|---|---|---|
| G5 announcement, September 20, 2026 | Two 24Gb-per-die LPDDR5X products in 496-ball and 245-ball packages | CXMT says both are in mass production |
| Broader LPDDR5X portfolio, October 28, 2025 | 12Gb and 16Gb standalone dies; packaged chips with 12GB, 16GB, and 24GB capacities; 16GB and 32GB LPCAMM modules; rates of 8533, 9600, and 10667 Mbps | The announcement says 8533 and 9600 Mbps products entered mass production in May 2025, while 10667 Mbps was available for customer sampling |
The 2025 portfolio announcement also says those products are backward-compatible with LPDDR5. That statement applies to the products described in that announcement; it does not establish compatibility details for G5 devices. CXMT’s October 2025 announcement does not tie the listed portfolio to G5.
What to watch next
To judge whether G5 is changing the competitive picture, look for information beyond a platform launch: independently tested product specifications, named devices or customers, disclosed capacity or shipments, and production data that clarify usable output. Until such evidence is available, the announcement is a meaningful claim of manufacturing progress, but not proof of market share gains, customer adoption, or lower memory prices.
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