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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsCreating a custom digital ASIC starts with a precise specification and a target manufacturing process—not with RTL alone. You then design and verify the logic, implement it using technology-specific rules, and prepare the layout for fabrication. These five tips cover the decisions that make that path more predictable, including when FPGA prototyping or open-source tools can help.
1. Turn the idea into measurable requirements
Write down what the chip must do and how you will decide whether it succeeds before settling on an architecture. A useful specification covers:
- Function: required operations, behaviors, and operating modes.
- Interfaces: signals, protocols, data widths, and connections to the rest of the system.
- Performance: throughput, latency, and timing targets.
- Power and area: limits that the design must meet.
- Operating conditions and test: the conditions it must tolerate and how you will check the finished chip.
Separate hard limits from preferences. This gives architecture choices and later verification a concrete target. The European Commission Joint Research Centre’s description of the ASIC design process begins with requirements and a design specification, then proceeds through systems design, RTL, logic design, verification, physical design, and design for manufacturing.
2. Choose the process early and confirm access
A digital design is not implemented against an abstract, interchangeable chip process. The target technology determines which cell libraries, models, constraints, and signoff recommendations the flow can use. Before committing to a design, contact the intended foundry or program to confirm that your project can access the process design kit (PDK), the required documentation, and the relevant implementation and signoff resources.
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For example, GlobalFoundries’ design-support page describes resources including PDKs, validated models, reference flows, documentation, and signoff collateral. CERN’s ASIC implementation flows are organized by target technology and note access arrangements for some technology-specific information. Its page identifies release v2026.08 and lists supported technologies including TSMC 28, 65, and 130 nm and OnSemi 180 nm; that is a listing for that flow release, not a general statement about foundry availability.
Confirm eligibility and access directly with the foundry or program: a public flow description does not itself provide the process files or authorize a tapeout.
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3. Plan verification alongside RTL
Translate the specification into checks while the design is being developed. Define expected behavior for normal operation, boundary conditions, and error cases; then track test coverage and unresolved issues as the RTL changes. Verification is not a final polish step: problems discovered after physical implementation can force costly changes to logic or constraints.
The JRC’s process description treats functional verification as a distinct part of ASIC development, while CERN’s flows include implementation signoff procedures and foundry-recommended settings. Those sources describe stages and resources, not a universal verification recipe. The right combination of checks depends on the chip’s function, interfaces, and risk; no single method should be assumed sufficient for every design.
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4. Prototype on an FPGA when it answers a real question
An FPGA prototype can let a team exercise a design in hardware before fabrication. It is most useful when the board has enough FPGA capacity and suitable interfaces for the behavior you want to evaluate. SoC Labs describes FPGA-based prototyping as an option for evaluating large SoCs.
Be clear about what the prototype can establish: it can help evaluate pre-silicon behavior, but it is not the final ASIC and does not establish that a design meets a foundry’s physical signoff requirements. Choose a board for the prototype’s actual capacity and interfaces rather than treating any FPGA board as a substitute for the target process.
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5. Plan the full path from RTL to fabrication
RTL describes the desired digital behavior; it is not the layout sent to a foundry. A typical digital implementation flow translates the RTL into logic for a particular technology, turns that logic into a physical layout, checks the result, and prepares manufacturing data. Expect to iterate: timing or physical results may require changes to the RTL, constraints, or architecture.
- Synthesize for the target technology. Map the RTL to cells supported by the chosen process and its libraries.
- Implement the physical design. Place and route the mapped design to create the physical geometry.
- Check and sign off the result. Evaluate timing and physical rules using the target flow’s requirements and collateral.
- Prepare the manufacturing handoff. Produce the layout data required by the foundry; SoC Labs identifies GDSII as the layout file needed for fabrication.
- Plan evaluation. Decide how the fabricated chip will be connected and tested against the specification.
SoC Labs outlines the RTL-to-GDSII progression, and CERN’s maintained flows provide technology-specific starting points, including scripts tailored to foundry and tool-vendor recommendations. A starting flow is not a replacement for the signoff requirements of the process you actually intend to use.
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Can open-source tools take a design all the way through?
Open-source tools can be useful for learning and implementation when the target technology and required flow resources are available. The OpenROAD project documents an RTL-to-GDS flow and reports more than 600 tapeouts in SKY130 and GF180 through full physical implementation for Google-sponsored Efabless MPW shuttle and ChipIgnite programs. The project page does not state a year for that total, and it is a project-reported figure, not an independently audited industry count.
Whether a flow fits a particular project depends on process access, signoff collateral, tools, and the level of support required. The sources do not establish universal cost or schedule comparisons.
Quick Recap
| Decision | Open-source or educational flow | Foundry-backed flow |
|---|---|---|
| Target process and PDK | Confirm the process and its required files are available for the project. | Confirm access and eligibility with the intended foundry or program. |
| Signoff | Check whether the flow includes the collateral and procedures required for the target process; availability is technology-specific. | Review the foundry’s documentation and signoff collateral for the selected process. |
| Tools and support | Check which tools, licenses, and support the project needs; the sources do not establish a universal cost comparison. | Confirm the tool flow, access terms, and support available for the project. |
| Best fit | Learning, prototyping, or implementation where the process and flow requirements match. | Projects that need resources and signoff aligned to the selected foundry process. |
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