Outdated Drivers Are Slowing You Down
One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchPC Slower Than It Used to Be?
A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11iTechGuides is reader-supported. When you buy through links on our site, we may earn an affiliate commission. As an Amazon Associate I earn from qualifying purchases. Learn more
At Hot Chips 2024, the XiangShan team presented two RISC-V processor tracks: Kunminghu, aimed at high performance in servers and data centers, and Nanhu, designed to emphasize power and area efficiency for industrial control. The presentation detailed Kunminghu’s wide, vector-capable architecture and reported SPEC CPU2006 results—but those Kunminghu and Nanhu benchmark scores came from RTL simulation, not measurements of shipping processors.
What is XiangShan?
XiangShan is an open-source RISC-V processor project that combines processor microarchitectures with a chip generator and development infrastructure. The project releases its design code and development flow under the MulanPSL2 license, according to its official project overview. Its official repository describes XiangShan as a high-performance RISC-V project and links to design documentation and a user guide.
The August 2024 presentation, “XiangShan: An Open-Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards,” was published at the 2024 IEEE Hot Chips 36 Symposium, as confirmed by the project’s publications page. The authors list affiliations at the Institute of Computing Technology, Chinese Academy of Sciences; University of Chinese Academy of Sciences; and Beijing Institute of Open-Source Chip.
What did XiangShan present at Hot Chips 2024?
The slides set out two architecture tracks with different priorities. The distinctions below describe the team’s intended positioning in that presentation, not proof that either design is equivalent to a commercial Arm processor.
#1 Best Overall
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
| Track | Stated emphasis and target | Profile and extensions listed | Status or evidence described | Positioning in the deck |
|---|---|---|---|---|
| Kunminghu | High performance; server and data-center systems | RVA-23, RISC-V hypervisor and vector extensions | Architecture details and performance figures were presented; the benchmark scores discussed below were from RTL simulation. | Compared in intended segment to Arm Neoverse N2; not a demonstrated equivalence. |
| Nanhu | Power/area efficiency; industrial-control applications | RVA-20 | The deck said Nanhu V2 had taped out and been tested; it separately reported a chip evaluation. | Compared in intended segment to Arm Cortex-A76; not a demonstrated equivalence. |
The presentation also described XiangShan as “The Linux of processor.” That is the deck’s characterization of the project, not a statement attributed to a named speaker.
What does the Kunminghu design include?
The Hot Chips deck describes a decoupled frontend with multilevel branch prediction and prefetching, feeding a six-wide decode, rename, and dispatch path. It lists a 160-entry reorder buffer and retirement of up to eight instructions per cycle. These are architecture specifications from the presentation, not independent test results.
Rank #2
- The ESP32-C5-WIFI6-KIT is a development board which is based on the ESP32-C5-WROOM-1 module for dual-band Wi-Fi and multi-protocol IoT gateway applications. 2.Equipped with 240 MHz RISC-V processor, 384 KB Static RAM, 16 MB Flash, and 8 MB PS-RAM, enables stable handling the concurrent tasks of multiple protocol stacks and running medium-load applications.
- The ESP32-C5 is a single-core RISC-V chip, supports dual-band Wi-Fi 6 (2.4GHz and 5GHz), and integrates BLE 5, Zigbee, and Thread protocols for flexible use as a smart home hub or cross-protocol communication gateway.
- Onboard batt. recharge management module, with reserved 3.7V MX1.25 Lithium batt. header for external batt. power supply. USB Type-C port, easier to use. Castellated module allows soldering directly to carrier boards, with rich peripheral interfaces.
- Supports multiple low-power operating modes, enabling flexible adjustment of the balance between communication range, data rate, and power consumption to meet the power requirements of various application scenarios
- Comes with Online Tutorial Usage Guide and Online Development Resource, Please check: n9.cl/ob241
Execution and vector resources
- Four integer ALUs.
- Four floating-point units and two floating-point dividers.
- Four vector units and one vector divider.
- V1.0 vector support with VLEN=128.
Memory system and pipeline
- Three load pipes and two store pipes.
- Capacity for 72 in-flight loads and 64 in-flight stores.
- 64 KB instruction cache and 64 KB data cache.
- Up to 1 MB of private L2 cache per core and up to 16 MB of shared L3 cache.
- A 13-stage pipeline diagram and a 16-cycle branch-misprediction penalty.
How fast are the reported XiangShan processors?
The deck’s Nanhu and Kunminghu SPEC CPU2006 scores were generated by RTL simulation using SimPoint-selected checkpoints. The team specified GCC 12 with -O3, RV64GCB, jemalloc, and DRAMsim3-modeled DDR4-3200 memory with 70 ns latency and dual-channel 2×64 memory. The cache setup was 64 KB instruction and data caches plus 256 KB L2 and 4 MB L3 for Nanhu; Kunminghu used 64 KB instruction and data caches plus 1 MB L2 and 16 MB L3. The figures below are project-reported results from that setup, not retail-system or silicon benchmark measurements.
Quick wins for a faster PC:
Repair Windows errors before they cause bigger problemsFix Now →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →| Design and condition | SPEC CPU2006 result | Evidence type |
|---|---|---|
| Nanhu at 2 GHz | SPECint2006 16.94; SPECfp2006 19.42 | XiangShan team RTL simulation, Hot Chips 2024 presentation, August 2024. |
| Kunminghu at 3 GHz | SPECint2006 44.00; 49.96 with compiler optimizations; SPECfp2006 47.63 | XiangShan team RTL simulation, Hot Chips 2024 presentation, August 2024. |
| Nanhu V2 | Approximately 10 SPEC CPU2006 points/GHz at 2.5 GHz | Separately labeled chip evaluation in the Hot Chips 2024 presentation; not the RTL simulation result above. |
Because the deck reports the Nanhu V2 chip evaluation separately from its simulation methodology, the two evidence types should not be conflated. The figures do not establish performance for a currently purchasable commercial processor.
Rank #3
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
How does XiangShan support design and verification?
The project’s scope goes beyond an individual processor core. The presentation describes a chip generator and development infrastructure, including the Minjie toolchain for microarchitecture design and verification. It emphasizes simulation-based verification and reports that the team reached Debian OS boot in simulation three months after the project’s conception.
- DiffTest compares RTL behavior with an ISA reference to help isolate functional errors.
- LightSSS uses simulation snapshots to reproduce debugging information.
The official repository describes Yanqihu as the first stable microarchitecture, Nanhu as the second, and Kunminghu as the third-generation architecture. That repository also provides a later project update: as of June 30, 2026, Kunminghu-V3 was actively evolving, while the project recommended Kunminghu-V2 for research, verification, or downstream applications. This is a later status update, distinct from the two-track roadmap shown in the 2024 talk. See the repository for current project guidance.
Rank #4
- ESP32-C6 1.47inch LCD Display Development Board supports 2.4GHz Wi-Fi 6 and Bluetooth BLE 5, integrates 4MB Flash. Onboard 1.47inch LCD screen can smoothly run GUI programs such as LVGL. Combined with various peripheral interfaces, suitable for the quick development of the HMI and other ESP32-C6 applications
- Equipped with a high-performance 32-bit RISC-V processor with clock speed up to 160 MHz, and a low-power 32-bit RISC-V processor with clock speed up to 20MHz
- Supports 2.4GHz Wi-Fi 6 (802.11 b/g/n) and Bluetooth 5 (LE), with onboard antenna, Built in 320KB ROM, 512KB of HP Static Random-Access Memory, 16KB LP Static Random-Access Memory and 4MB Flash memory
- Onboard 1.47inch LCD display, 172×320 resolution, 262K color. Built-in RGB LED with clear acrylic sandwich panel for cool lighting effect
- Adapting multiple IO interfaces, integrates full-speed USB port. Onboard TF card slot for external TF card storage of pictures or files. Supports accurate control such as flexible clock and multiple power modes to realize low power consumption in different scenarios
Is XiangShan available as a chip?
XiangShan’s design code and development flow are open source, but that does not mean the presented processors are available as retail chips. The Hot Chips slides reported tape-out and testing for Nanhu V2 and gave a separate chip-evaluation figure; they do not establish commercial availability of a processor, board, or product. The Kunminghu benchmark numbers highlighted above are RTL simulation results.
Quick Recap
Best Value
- 🍊[High-Performance RISC-V Development Board]: Orange Pi RV2 features an octa-core RISC-V processor with integrated AI acceleration. It delivers 2.0 TOPS AI performance, with single-core CPU performance surpassing ARM A55 by over 30%.
- 🍊[Supports AI Model Deployment]: Orange Pi RV2 provides AI computing power through CPU core integration, enabling fast AI model deployment and seamless compatibility with all major AI ecosystems, supporting various edge AI large models.
- 🍊[Flexible Memory & Storage Options]: Equipped with 2GB/4GB/8GB LPDDR4X RAM and supports optional eMMC modules (32GB/64GB/256GB) for enhanced storage flexibility.
- 🍊[Comprehensive Connectivity]: Orange Pi RV2 offers HDMI output, GPIO interface, USB 2.0 & 3.0, Gigabit Ethernet, 3.5mm headphone jack, and two M.2 M-Key slots (PCIe 2.0 2-Lane) for NVMe SSD expansion. And comes with Wi-Fi 5.0 + Bluetooth 5.0 (BLE) for seamless wireless connectivity.
- 🍊[Wide range of Applications]: Orange Pi RV2 is highly versatile, making it ideal for NAS, smart robotics, smart home, industrial control, edge computing, and commercial electronics.
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
