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On September 11, 2000, TSMC said it had moved its planned customer offering of 0.13-micron process technology forward by one quarter and remained on schedule for initial 300-mm wafers. The dates in the report were targets and forecasts, not confirmation that the milestones were later achieved.
What did TSMC announce about 0.13-micron technology?
TSMC said it had accelerated its plan to offer 0.13-micron process technology to customers by one quarter. Its then-president, F.C. Tseng, said risk production was scheduled for October 2000. The report explains that risk production meant qualifying foundry wafers for customer designs.
TSMC planned to ship its first 0.13-micron foundry wafers in volume in the first quarter of 2001. These were schedules reported at the time; the September 2000 account does not establish whether either date was met.
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What was the 300-mm wafer plan?
The report described two stages: a pilot line at Fab 6, followed by planned production facilities.
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Fab 6 pilot line
TSMC expected its first 300-mm wafers from a pilot line inside Fab 6 in Tainan in December 2000. Tseng said the company was on track to produce its first wafers by year-end.
Planned production fabs
TSMC was building two 300-mm production fabs: Fab 12 in Hsinchu and Fab 14 in Tainan. The company expected volume fabrication for foundry customers to begin in those facilities the following year. That was a forecast in 2000, not evidence in this report that production began as planned.
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- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
What did “pulls up” mean?
It referred to TSMC moving its planned 0.13-micron customer offering schedule forward by one quarter. The article does not give a revised date for every development milestone; it specifically reports an October 2000 risk-production schedule and a first-quarter 2001 volume-shipment plan.
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The announcement came amid competition among foundries, particularly TSMC and UMC, to offer advanced process technology and 300-mm capability. Tseng attributed a lead to customer feedback, saying, “Our customers tell us that we’re ahead of our competitors right now,” and added, “We will be the first in Taiwan to have a 300-mm fab,” and “We will be among the first group of chip makers in the world with a 300-mm fab.” Those were Tseng’s claims; the article says UMC officials were unavailable for comment.
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Tseng also said, “A lot of chip makers claim they have 0.13-micron technology, but the question is if anybody will use it,” and, “We have some demand from our high-end customers.” The comments distinguish announcing a process from qualifying it for customer designs and securing demand, but the article provides no independent measure of customer adoption.
What did TSMC say about capacity?
Tseng described capacity as tight and business for 2001 as firm: “Capacity is tight right now,” and “For 2001, business is pretty firm.” The report also said TSMC had recently stated it was fully booked until at least the end of 2001. These statements describe the company’s position as reported in 2000 and say nothing about its capacity today.
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What the 2000 report does—and does not—establish
EE Times’ September 11, 2000 report by Mark LaPedus is a contemporaneous account of plans and statements attributed to TSMC president F.C. Tseng. It documents the announced schedules, the Fab 6 pilot-line expectation, and the planned Fab 12 and Fab 14 facilities. It does not verify subsequent completion, production volumes, or comparative performance. Read its dates as historical forecasts rather than current roadmap information.
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EE Times: “TSMC pulls up 0.13-micron technology, stays on track with 300-mm wafers”
Quick Recap
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- 5 x 5 inches, 0.67 ounces, 0.03 inches thick. Some wafers are marked with alignment marks.
- The pattern is produced by light diffraction, and its reflective appearance changes with the viewing angle.
- Silicon wafers are fragile—please handle with care.
- Circuit details can be examined under a microscope.
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