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Hold-up time is how long a power supply unit (PSU) keeps its DC outputs within specification after AC input is interrupted. Power Good (PWR_OK or PG) is a logic signal that tells the motherboard when the PSU’s key outputs are in range—and warns it before they can no longer be guaranteed. Hold-up time is stored-energy ride-through, not backup power; PWR_OK is a status signal, not a source of power.

What hold-up time means

A PSU stores energy, principally in its input capacitors, so it can continue delivering regulated DC for a short time after incoming AC disappears. Hold-up time is the interval during which those outputs remain within their specified limits. It is meant to bridge brief interruptions, such as a missed AC cycle or the transfer time of some UPS units, not to keep a computer running through a sustained outage.

The figure depends on the PSU’s input voltage and frequency, output load, and the test conditions used. A hold-up-time number without those conditions is difficult to compare with another PSU’s figure.

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What the PWR_OK signal tells the motherboard

Intel’s 2023 ATX Version 3 Multi Rail Desktop Platform Power Supply Design Guide defines PWR_OK as a signal the PSU asserts high when the +12 V, +5 V, and +3.3 V outputs are within their regulation thresholds and the converter has enough stored mains energy to guarantee continued operation within specification for the required duration. If a monitored rail drops below its threshold, or AC has been absent long enough that operation can no longer be guaranteed, the PSU deasserts PWR_OK low. The motherboard can use that warning for shutdown or reset handling before the DC outputs are lost.

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PWR_OK is a digital interface, not extra stored energy. Intel lists it as +5 V TTL-compatible. ATX 3 and ATX12VO tables specify a low level below 0.4 V, a high level from 2.4 V to 5 V, a 1 kΩ high-state output impedance, and maximum ripple/noise of 400 mV peak-to-peak. These are interface limits for system design; they do not establish measured performance for any particular retail PSU.

How long should a PSU hold up?

There is no single millisecond figure that applies to every ATX revision and load. Intel’s 2023 ATX12VO guide gives different values for full-load hold-up and also distinguishes total output hold-up from the PWR_OK warning interval. Intel’s older ATX12V Version 1.1 guide specifies another condition. Compare figures only alongside their specification revision and test load.

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Specification and condition Published timing What the figure describes
Intel ATX12VO, 2023 12 ms at 100% full load (required); 17 ms at 80% full load (recommended) Hold-up time at the stated load
Intel ATX12VO, 2023 T5: greater than 11 ms required and greater than 16 ms recommended PWR_OK hold-up interval
Intel ATX12VO, 2023 T6: greater than 1 ms Delay from PWR_OK becoming inactive to DC loss
Intel ATX12V Version 1.1 design guide; publication year not stated in source metadata 17 ms minimum at maximum continuous load Hold-up time
Intel ATX Version 1.1 design guide; publication year not stated in source metadata PWR_OK delay: 100–500 ms; rise time: no more than 10 ms; power-down warning: at least 1 ms Signal timing

The ATX12VO table separates total hold-up (T5+T6) from the PWR_OK warning interval. The signal transition is therefore not the same event as complete DC output loss. Do not treat timing values from different revisions, loads, or timing definitions as interchangeable.

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What to check in a PSU specification

  • ATX revision: Identify whether the stated requirement is for older ATX12V, ATX 3.x, or ATX12VO; revisions can define different timing and test conditions.
  • Load at measurement: Check whether hold-up is reported at 100% load, 80% load, or another specified level.
  • Input conditions: Look for the input voltage and frequency used for the measurement.
  • PWR_OK timings: Check the signal delay, rise time, and AC-loss warning interval as well as total hold-up.
  • Published evidence: Prefer a manufacturer datasheet that gives measured timing data and tolerances over an unlabeled marketing claim.

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