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ASML High-NA EUV is a family of extreme-ultraviolet lithography systems, called TWINSCAN EXE, that uses 0.55 numerical aperture optics to print smaller patterns than ASML’s earlier 0.33-NA EUV systems. It still uses 13.5 nm light. ASML specifies 8 nm resolution for the EXE:5000, but that is an optical-system specification—not a guarantee that every finished chip feature measures 8 nm.
What “High-NA EUV” means
NA stands for numerical aperture, a measure of an optical system’s ability to collect and focus light. ASML’s EXE platform has a numerical aperture of 0.55, compared with 0.33 for its NXE EUV platform. Both use EUV light at a wavelength of 13.5 nm. The higher NA improves resolution without requiring a shorter wavelength.
ASML’s first High-NA system is the TWINSCAN EXE:5000. Its 0.55-NA projection optics use an anamorphic design: the mask image is demagnified 4× in one direction and 8× in the other. ASML says this lets chipmakers retain traditionally sized reticles despite the larger optics. The exposure field is half the NXE field, so the system also uses faster wafer and reticle stages.
How High-NA compares with earlier EUV
| Characteristic | ASML NXE EUV | ASML EXE High-NA EUV |
|---|---|---|
| Numerical aperture | 0.33 (ASML and imec platform descriptions) | 0.55 (ASML and imec platform descriptions) |
| Wavelength | 13.5 nm | 13.5 nm |
| Resolution figure | Not stated in the cited ASML and imec descriptions | 8 nm for EXE:5000, per ASML |
| Mask-image reduction | Not stated in the cited descriptions | 4× in one direction and 8× in the other, per ASML |
| Exposure field | Reference field size | Half the NXE field, per ASML |
The 8 nm figure is not interchangeable with a printed feature width, line-and-space pitch, or a process-node label. The final wafer pattern depends on the resist, underlayers, mask, etch and integration process as well as the scanner optics. For example, imec reported a 2024 demonstration of single-print 16 nm-pitch lines and spaces using an EXE:5000 and optimized metal-oxide resist. It also reported 24 nm-pitch contact holes and pillars. In later work, imec reported metallized lines at 20 nm pitch and ruthenium lines at 18 nm and 20 nm pitch using direct metal etch. These are process-specific results, not alternative measurements of the EXE:5000’s nominal 8 nm resolution.
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Why chipmakers use it
A higher-NA scanner is designed to print finer patterns in a single exposure, potentially reducing the need to split a layer across two or three patterning steps. Fewer steps can reduce process complexity, cycle time, opportunities for defects and demand for fab space. The gains depend on the design and process integration; they are not automatic for every layer or chip.
ASML says the EXE:5000’s 8 nm resolution enables single-exposure printing of features 1.7 times smaller and transistor density 2.9 times higher than possible with NXE systems. Those are ASML’s platform comparisons, not independent measurements of every production design. ASML positions EXE for advanced logic beginning at the 2 nm node; imec describes its EXE:5200 research platform as supporting development of sub-2 nm logic and high-density memory. “2 nm” and “sub-2 nm” are process-node labels, not literal measurements of a transistor feature.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Where High-NA EUV stands in 2026
High-NA EUV has moved beyond research demonstrations, but production use remains selective. On July 15, 2026, ASML said Intel Foundry had entered high-volume manufacturing for a subset of Panther Lake processors, part of Intel Core Ultra Series 3, using High-NA EUV on specific layers of Intel 18A. Intel and ASML said those layers were dual-qualified, and the product shipped at yields matched to NXE.
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On September 7, 2026, Intel and ASML reported that more than one million wafers had been processed across early tool certification and testing, research and development, and volume production on selected layers for that Panther Lake subset. The total therefore is not one million commercial-production wafers. Intel said overlay, throughput and availability were meeting its expectations.
ASML’s 2025 annual report said the EXE platform was expected to start supporting high-volume manufacturing in 2027. That roadmap statement predates the 2026 reports of Intel’s selected-layer production use. The statements describe different scopes: limited insertion on particular Intel layers is not the same as broad adoption of the platform across products and manufacturers.
EXE:5000 and EXE:5200B
ASML’s 2025 annual report says it shipped the first EXE:5200B in early April 2025, ready for high-volume manufacturing use. ASML reports productivity of 175 wafers per hour for that system, 60% higher than EXE:5000, attributing the improvement to an upgraded EUV light source. These are ASML’s reported platform figures, not a guarantee of throughput under every fab’s production conditions.
Imec’s EXE:5200 research system
Imec announced on March 18, 2026, that its EXE:5200 had arrived in its 300 mm cleanroom in Leuven, Belgium. At the time, imec anticipated full qualification by Q4 2026; the announcement itself does not confirm that qualification was completed. Imec described the system as a platform for developing High-NA patterning applications for sub-2 nm logic and high-density memory.
Quick Recap
What the specifications do—and do not—tell you
- NA and wavelength describe the optics. The move from 0.33 to 0.55 NA improves resolution while the wavelength remains 13.5 nm.
- Resolution is not a chip dimension. A scanner’s resolution specification does not say that every printed line, contact or transistor feature has that size.
- Pitch is a different measurement. Imec’s line-and-space demonstrations report pitch, which describes the repeating spacing of a pattern; it is not the same as the width of an individual line.
- Node names are not ruler measurements. A 2 nm or sub-2 nm label identifies a process generation, not a literal feature width.
- Manufacturing readiness has levels. Research demonstrations, system qualification, selected-layer production and broad high-volume adoption are distinct milestones.
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