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Google’s TPU matrix unit is formally called the Matrix Multiplication Unit (MXU). It is a component inside a TPU TensorCore that performs matrix multiply-accumulate operations—the core arithmetic in many machine-learning workloads. The MXU is not a whole TPU chip: it works alongside the TensorCore’s vector and scalar units.
What does MXU mean in a TPU?
MXU stands for Matrix Multiplication Unit. Google describes it as the part of a TensorCore that handles matrix multiplication, accumulating partial results as it computes. Matrix operations are central to many neural-network tasks, so the MXU supplies most of a TensorCore’s compute power for matrix-heavy work. Google Cloud’s TPU architecture documentation describes the MXU as a systolic array of multiply-accumulators.
How does the TPU MXU work?
An MXU is a systolic array: multiply-accumulate units are connected so data and intermediate results move from one unit to the next in a regular pattern. Rather than repeatedly fetching and storing each intermediate value, the connected units pass partial results through the array as the computation proceeds. For a matrix product, data and parameters enter the computation path from high-bandwidth memory; the units multiply values and accumulate partial products into the output. This design is specialized for matrix arithmetic rather than general-purpose computing. Google’s account of its first TPU provides historical context for the design.
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A TPU chip contains one or more TensorCores, and each TensorCore contains one or more MXUs as well as a vector unit and a scalar unit. Counts depend on the TPU generation: Google specifies four MXUs in each TPU v5p TensorCore. Therefore, “MXU,” “TensorCore,” “TPU chip,” and a cloud TPU allocation refer to different levels of the system, not interchangeable parts. Google’s architecture documentation gives model-specific details.
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MXU dimensions and precision vary by generation
The array size is not a universal TPU specification. Google’s architecture documentation lists these dimensions:
| TPU generation | Multiply-accumulators per MXU |
|---|---|
| TPU v6e and TPU7x | 256 × 256 |
| TPU versions before v6e | 128 × 128 |
Google’s current architecture description says the MXU multiplies bfloat16 inputs and accumulates in FP32. Confirm the documentation for the particular TPU model before applying that precision description to a specific deployment, since hardware configurations change.
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Older specifications should not be read as current-model figures. In its article on the original TPU, Google reported a 256 × 256 array containing 65,536 ALUs. For that original design, Google also reported 65,536 8-bit integer multiply-and-adds per cycle at 700 MHz, or 92 tera-operations per second under its stated counting convention. Those are historical, vendor-reported figures for the first TPU—not performance specifications for current Cloud TPU models.
When does MXU performance matter?
The MXU matters most when a workload spends much of its time doing matrix calculations. Google’s introductory TPU guidance identifies matrix-heavy models, large training runs, and large embedding workloads as examples that can suit TPUs. Google’s TPU introduction also explains that workload shape and operations affect execution.
Frequent branching, extensive element-wise work, custom operations in the main training loop, or arithmetic that needs unsupported or less suitable precision can reduce TPU suitability or leave the MXU underused. A large MXU array alone does not show whether a whole model will run efficiently.
Why matrix dimensions can affect utilization
XLA compiles the workload graph for TPU execution and tiles matrix multiplication into smaller blocks. Dimensions affect how those tiles map to the array; some may be padded. Google’s introductory material discusses alignment with the documented 128 × 128 systolic array, but this is not a universal performance guarantee. The outcome depends on the model, compiler, and TPU generation.
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What the MXU specification does—and does not—tell you
Array dimensions describe a hardware component, not end-to-end model speed. To assess a TPU for a real task, account for the workload’s matrix share, numerical precision, software and operation support, and the surrounding memory and interconnect design. A comparison with a GPU or CPU requires controlled end-to-end measurements on the target workload; the MXU specification by itself cannot establish a universal winner.
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- A USB accessory that brings machine learning inferencing to existing systems. Works with Raspberry Pi and other Linux systems
- Performs high-speed ML inferencing: the on-board edge TPU Coprocessor is capable of performing 4 trillion operations (tera-operations) per second (tops), using 0.5 watts for each tops (2 tops per watt). For example, it can execute state-of-the-art mobile vision models such as mobilenet V2 AT 400 FPS, in a power efficient manner
- Works with Debian Linux: connects to any debian-based Linux system with an included USB 3.0 Type-C cable
- Supports tensorflow Lite: no need to build models from the ground up. Tensorflow Lite models can be compiled to run on the edge TPE
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