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Honda and Renesas are developing a high-performance system-on-chip (SoC) for core computing systems in future Honda 0 Series electric vehicles. Announced on January 8, 2025, the design is intended to support functions including automated driving, powertrain control and cabin comfort. Its headline figures—2,000 TOPS and 20 TOPS/W—are targets, not measured results from a finished production chip.
What Honda and Renesas are developing
The companies announced a development agreement at CES 2025. The planned SoC is for core electronic control units (ECUs) in future Honda 0 Series EVs. Honda describes the intended computing role as spanning automated driving and advanced driver-assistance systems (ADAS), powertrain control and comfort functions. Honda’s January 8, 2025 announcement says the target application is Honda 0 Series models launching in the late 2020s.
An SoC brings computing functions together in a chip or chip package. In Honda’s envisioned vehicle architecture, a high-performance core ECU would coordinate demanding software functions rather than leaving each function to an isolated controller. The announcement describes a development plan; it does not establish that a production chip has been completed or specify the final ECU configuration of any particular vehicle.
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The design pairs Renesas’s general-purpose Gen 5 R-Car X5 SoC series with a Honda-optimized AI accelerator. The companies say the design will use multi-die chiplet technology and TSMC automotive 3-nm process technology. In a chiplet approach, different dies can provide different functions and be combined into one design; here, the accelerator is Honda-optimized while the R-Car X5 series supplies the Renesas component.
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Honda and Renesas say the chiplet approach can support customization and later functional or performance upgrades. That is an intended design benefit, not evidence that a particular upgrade has been delivered or that a vehicle owner will be able to upgrade hardware after purchase. The joint announcement says chiplets allow flexibility to create customized solutions and offer future upgrades.
What 2,000 TOPS and 20 TOPS/W mean
Honda and Renesas announced a target of 2,000 TOPS for AI performance and 20 TOPS/W for power efficiency. TOPS means trillions of operations per second; TOPS/W expresses operations per second per watt. The companies qualify the 2,000-TOPS target as based on a sparse AI model, and Renesas describes it as its estimate as of January 2025. Neither figure is a reported production measurement of the finished Honda chip.
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TOPS alone does not show how well an automotive system will perform in real ADAS or automated-driving workloads. Comparisons require the workload and model basis, whether the number is a target or measured result, how power efficiency is calculated, and how the chip is integrated and deployed. The cited announcement does not provide a final production specification or independent benchmark results, so the targets should not be read as proof that the planned system outperforms another automotive compute platform.
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When the chip could appear in Honda vehicles
Honda’s stated plan is to use the SoC in 0 Series models launching in the late 2020s. That timing is distinct from Honda’s broader 0 Series launch schedule: an overview current as of January 2025 said the model line was scheduled for global launches starting in 2026. Honda described the initial models as using a domain-centralized architecture, with a single high-performance central ECU planned for later generations. See Honda’s SDV overview for that broader architecture and vehicle timeline.
The available announcements do not establish a confirmed delivery date, the current milestone status of Renesas’s project, or final specifications. They therefore support describing a planned application and target window—not claiming that a specific 0 Series vehicle is confirmed to receive this exact chip on a particular date.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How the Renesas agreement fits Honda’s SDV strategy
Honda presents the SoC as one part of a wider software-defined vehicle (SDV) strategy that includes ASIMO OS, over-the-air (OTA) updates and centralized vehicle computing. The idea is to make software functions and updates central to how vehicle features are managed, while high-performance computing supports multiple vehicle domains. Honda’s January 2025 overview also forecast that SDV AI performance requirements by 2030 would be 500 times higher than in 2024; that is Honda’s forecast, not an independently verified industry statistic.
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In February 2026, Honda announced separate research and co-development with U.S.-based Mythic focused on neuromorphic technology, including analog compute-in-memory. That announcement does not say the Mythic project replaces or changes the Renesas agreement. The cited materials do not establish how the two efforts may relate in future products. Honda’s February 4, 2026 Mythic announcement describes the separate initiative.
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- Cool light and sound: There is a three-position switch on the bottom of the car. When in the middle gear, the front and rear lights are on continuously. When in the sound gear, pressing on the front of the car triggers sound and light effects, pressing the horn also makes a realistic horn sound.
- Exquisite design：It has detailed interior. The doors, hood and trunk can be opened. Mirrors can be folded. The wheels simulates shock absorption.
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