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Cadence says its configurable Tensilica ConnX B20 DSP can deliver up to 30 times the performance of the older ConnX BBE32EP for communication applications, including appropriate parts of 5G workloads. That is a vendor-reported maximum for selected signal-processing work—not a claim that every 5G system, phone, or network runs 30 times faster.
What is the Tensilica ConnX B20?
The ConnX B20 is configurable digital signal processor (DSP) intellectual property from Cadence. Rather than a retail processor or consumer 5G modem, it is a design that a chipmaker can license, configure, and integrate into a system-on-chip (SoC) for signal-processing tasks. Cadence positions the ConnX family for communications, radar, and lidar applications. Cadence’s 2019 announcement describes the B20’s communications focus, while its ConnX family page and datasheet cover the wider product family.
Cadence describes ConnX processors as SIMD vector processors with VLIW execution, enabling parallel operations. Designers can select configurable vector packages and, depending on the SoC, use programmable DSP processing alongside dedicated hardware accelerators. The family’s software compatibility can also matter when choosing among ConnX members, though a particular design’s configuration and software still need to be evaluated.
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What does “up to 30X” mean for 5G?
In its February 2019 announcement, Cadence said communication-application performance could be “as much as 30X higher” than the ConnX BBE32EP. It separately described “up to 30X improved performance in the appropriate parts of 5G communications applications.” The comparator is therefore the older BBE32EP, and the scope is selected parts of communication workloads—not all 5G processing or end-to-end network performance. Cadence’s announcement does not provide a reproducible public benchmark configuration for independently checking that maximum; the figure should be treated as a Cadence claim, not an independently validated result.
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A DSP’s contribution depends on which algorithms it runs and how the core is configured, as well as the surrounding memory system, software libraries, and power budget. A faster result on a specific kernel would not, by itself, establish a similar gain for a complete baseband, a full SoC, or a user’s 5G connection.
What B20 specifications does Cadence publish?
Cadence’s family datasheet lists the following B20 throughput figures. They are vendor-published IP specifications, not measurements of whole-system throughput; they should not be read as capabilities that necessarily appear simultaneously in every configuration. See Cadence’s ConnX family datasheet.
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| Specification | Cadence-published B20 figure | How to interpret it |
|---|---|---|
| Vector/memory width | 512 bits | Published architectural width; system performance also depends on configuration and memory integration. |
| 16-bit integer multiply-accumulate | 128 16-bit-by-16-bit MACs | Throughput-table figure for the DSP IP, not a general application benchmark. |
| 32-bit integer multiply-accumulate | 32 32-bit-by-32-bit MACs | Vendor throughput specification. |
| Single-precision floating-point | 32 single-precision FP FMAs | Vendor throughput specification. |
| Half-precision floating-point | 64 half-precision FP FMAs | Vendor throughput specification. |
| Double-precision floating-point | 16 double-precision FP FMAs | Vendor throughput specification. |
The 2019 announcement also describes operation at 1.4GHz or greater on a 16nm process, a deeper pipeline, an optional 32-bit floating-point vector MAC, extended floating-point options, and communication-focused forward error correction acceleration. Those details describe Cadence’s announced design options; they do not guarantee a given clock rate or feature set in every customer’s finished chip. Cadence’s B20 announcement
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Cadence engineering blogger Prasath Kumaraveeran of Fraunhofer IIS/EAS described a custom B20 implementation that completed a complex 4K FFT in 768 cycles, compared with 2,070 cycles for the ConnX B20 library in that implementation. The approach used Tensilica Instruction Extensions (TIE) and parallel FIFO queues. This is a particular FFT implementation and comparison, not a general benchmark for every B20 configuration or workload. Read the Cadence blog post.
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How should chip designers evaluate the B20?
Cadence’s 5G technical brief frames DSP selection as a balance among performance, memory, energy, and cost. For a real SoC decision, compare options using the intended workloads and target conditions rather than relying on a headline maximum.
- Workload performance: Measure cycle counts and throughput on the actual signal-processing kernels the design needs.
- Precision: Check numerical requirements and whether the available integer or floating-point options fit the algorithms.
- Memory and integration: Assess bandwidth, memory behavior, interfaces, and how the DSP connects to the rest of the SoC.
- Power and area: Evaluate energy use and silicon area under the target operating conditions.
- Configuration and software: Review configurable options, dedicated accelerators, compiler and library support, and compatibility or migration needs.
Cadence also reports that Metanoia used multiple ConnX 230 DSP instances in a 5G low-PHY software-defined-radio platform. That is an example involving another ConnX family member, not evidence of B20 adoption or validation of the B20’s 30X claim. Cadence’s Metanoia announcement
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