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A RISC-V standard is a foundation, not a finished product. In an April 10, 2026 EE Times podcast, host Sally Ward-Foxton and Marc Evans, Andes Technology’s director of business development and marketing, describe commercialization as the coordinated work of selecting CPU IP, integrating interconnect and debug hardware, building software, and meeting application-specific requirements.
What does it take to ship a commercial RISC-V product?
Evans’ central argument is that standardization reduces uncertainty for software developers, but it does not remove the engineering needed to build a chip. A shipping product combines several layers:
- A compatible ISA target: Profiles such as RVA23 and extensions such as vectors can give software teams a clearer, more vendor-independent baseline.
- CPU IP: The processor implementation must fit the performance, power, area, security and product requirements.
- Integration infrastructure: Evans specifically names network-on-chip and debug infrastructure as components customers assemble around the CPU.
- Software: Boot code, operating-system support, drivers, tools and applications must run on the resulting implementation.
- Product qualification: Automotive and other regulated uses add process, safety and system-level obligations.
“So from that perspective, I think the standardization is highly required,” Evans says. His point is that a common compatibility base helps software investment; it is not that an ISA standard alone makes a chip ready to ship.
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How standards help—and where they stop
RVA23 and vector extensions
Ward-Foxton asks Evans about the RVA23 profile and technical milestones. He treats RVA23 (spelled “RVA 23” in the transcript) and vector extensions as important steps toward a more predictable software target. The episode does not establish which particular products or software packages conform, so those details should not be inferred from the discussion.
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Standards lower compatibility risk
With a standardized base, developers can target an interface intended to remain compatible across vendors. That can make it easier to reuse software knowledge and tooling rather than rewriting everything for each proprietary processor.
Standards do not perform the integration
Customers still decide how the processor connects to memory, accelerators, peripherals, security blocks and debug facilities. Evans describes this assembly work as continuing to move “upstream a little more.” The resulting integration choices, not just the ISA, determine how a particular chip behaves.
The practical commercialization workflow
- Define the workload and software boundary. Establish whether the product runs a tightly controlled software stack or must support a broad ecosystem of applications.
- Select and configure CPU IP. Choose the required cores, extensions and customization options for the workload and constraints.
- Build the surrounding subsystem. Integrate network-on-chip, memory, peripherals, accelerators, security functions and debug infrastructure.
- Bring up the software. Port firmware, operating-system components, drivers and development tools to the actual implementation.
- Validate the complete design. Test hardware and software together, then address the reliability, performance, security or safety requirements of the target market.
- Qualify and manufacture. Product-level evidence, production controls and system integration are required before volume deployment.
Evans says software is generally easier when a customer controls its software footprint. Support for open applications is progressing, but the interview presents it as work still underway rather than a solved problem.
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Where RISC-V readiness differs by application
Evans offers qualitative, vendor-side observations rather than measured market shares. The following comparison captures the decision axes he discusses.
| Deployment setting | What Evans emphasizes | Key commercial challenge |
|---|---|---|
| Embedded products, from hearables to network communications | Strong volume and penetration | Efficient integration across many cost-, power- and function-constrained designs |
| Data-center accelerators | Large designs, especially where the customer controls its software footprint | Co-designing substantial hardware with a software stack the operator can manage |
| AI systems | Extensive use of ISA customization | Choosing useful specialization without making software and verification unmanageable |
| Automotive AI and physical AI | Potential for task-specific tuning | Meeting automotive development and safety obligations in a complete implementation |
| Automotive infotainment | Likely to take longer because it resembles a broad app-store environment | Supporting wide application compatibility rather than only a controlled workload |
These are Evans’ assessments from the interview, not independently measured forecasts or industry-wide rankings.
What are the biggest hurdles?
Software breadth
A tightly controlled product can tailor its operating environment to one chip. A platform expected to run many third-party applications needs broader compatibility, mature tools and dependable support. That distinction affects both schedule and engineering cost.
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- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
Integration complexity
CPU IP is only one subsystem. Interconnect, memory, debug, peripherals, accelerators and security features must work together and be verified as a whole. Integration decisions can erase the apparent simplicity of adopting a standardized ISA.
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Customization trade-offs
Custom instructions or extensions can improve a specialized AI or signal-processing workload. They also create additional compiler, toolchain, software-porting and verification responsibilities. The commercial question is whether the workload benefit justifies that long-term maintenance.
Qualification and ecosystem confidence
Customers need confidence that the implementation, tools and supply chain will remain supportable over the product’s life. Standardization helps with the software-facing part of that confidence, while vendors and chip teams must provide the rest.
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- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
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Why automotive safety applies to the implementation
“So I don’t see there’s an automotive safety qualification for an ISA,” Evans says. In his account, safety qualification concerns a concrete processor implementation, its development process and ultimately the vehicle-level system—not the instruction-set definition in isolation.
Evans says Andes has obtained process-level systematic certification and designs products within that process for product certification. He also mentions Quintauris and a real-time reference platform. Those are statements made in the sponsored interview; the episode does not independently verify certification records or establish that every Andes product has a particular automotive approval.
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- Which implementation and configuration is being used?
- What development, verification and change-control processes govern it?
- What evidence is available for the required safety goals?
- How does the processor fit into the certified vehicle-level system?
What separates a successful RISC-V program from a failing one?
The interview’s practical dividing line is not simply choosing RISC-V. Successful teams align the ISA, CPU configuration, integration plan and software strategy with a specific product requirement. They know how much application compatibility they need, where customization creates value, and which qualification obligations apply.
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Programs are more exposed when they treat the ISA as a substitute for ecosystem work—assuming that a standard automatically supplies production-ready interconnect, debug, tools, operating-system support or safety evidence. Those elements still have to be selected, integrated, tested and maintained.
How should the Andes shipment figure be read?
Andes’ episode-page promotional copy says “Over 19 billion Andes-powered SoCs.” In the interview, Evans says “19 or 20 billion” SoCs shipped. Both figures are Andes statements, and the difference in precision matters: the episode does not independently audit the number, and it is not a total for all RISC-V products or the semiconductor industry.
The figure is best understood as a company shipment claim used to describe Andes’ commercial history, not as proof that every RISC-V design is equally mature or that a particular application is ready without additional engineering.
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