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TSMC’s 32 nm announcement in 2007 described a technology under development, while its 28 nm roadmap in 2008 forecast production for 2010. TSMC later announced 28 nm volume production in October 2011. Those milestones describe foundry process offerings for chip designers—not consumer chip models—and the nanometer labels alone do not tell you which chips used them or how a particular chip performs.
What did TSMC announce about 32 nm?
On December 11, 2007, TSMC announced that it had developed 32 nm technology with analog and digital functionality and demonstrated a fully functional 2 Mb SRAM test chip. The company characterized the platform as targeting low power, high density, and manufacturing margins, with system-on-chip (SoC) applications aimed at mobile devices. This was a development milestone, not an announcement that a retail device or consumer chip was available.
In June 2008, TSMC announced Unified DFM, a design-for-manufacturing framework targeting 32 nm and smaller geometries. The framework brought manufacturing information into customer design flows through a design kit, software engine and API, process data, and models. It was design infrastructure, not a separate process node or consumer product. TSMC’s June 2008 announcement described the framework’s scope.
What did TSMC’s 28 nm roadmap say?
On September 29, 2008, TSMC announced a 28 nm full-node family with high-k metal gate (HKMG) and silicon oxynitride (SiON) options. Its release forecast initial production in the first quarter of 2010; that was a forecast, not a report that production had already begun. The company positioned variants for different targets: 28LPT for portable consumer and wireless applications, and 28HP for performance-focused CPU, GPU, and FPGA applications. These were TSMC’s stated target uses and positioning.
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In August 2009, TSMC said its low-power HKMG derivative, 28HPL, was expected to enter risk production in the third quarter of 2010. The company cited cell phones, wireless communication, and portable consumer electronics as intended application areas, while distinguishing 28HPL from SiON-based 28LP. “Expected” and “risk production” matter: neither phrase means volume production had been achieved at that point.
That 2009 announcement also reported a functional 64 Mb SRAM with good functional yield, a 0.127 µm² SRAM cell, and raw gate density of up to 3,900 kGate/mm² for the described 28 nm dual/triple gate-oxide technology. These are company-reported figures for that specific technology context, not universal measurements for every 28 nm process. The 2009 release contains the original scope and qualifications.
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- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
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When did TSMC 28 nm enter volume production?
On October 24, 2011, TSMC announced that 28 nm was in volume production. It listed 28HP, 28HPL, and 28LP as already in volume production, and said 28HPM was expected to be ready by year-end. The same release reported more than 80 customer product tape-outs at that time. That count is a dated 2011 figure, not a current customer or product total. A tape-out is a design milestone; it does not identify a chip sold to consumers or establish that every design shipped.
The production announcement followed the earlier roadmap forecast, but the milestones are distinct: a development announcement, a forecast, risk production, and volume production do not mean the same thing. TSMC’s October 2011 release is the source for the variants and their stated status on that date.
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How should you compare 28 nm and 32 nm?
| Question | What the announcements establish |
|---|---|
| What was announced? | 32 nm development with functional analog/digital capability and a 2 Mb SRAM test chip in 2007; a 28 nm full-node family with HKMG and SiON options in 2008. |
| What application targets were stated? | TSMC described 32 nm SoC capability for mobile applications. For 28 nm, the company assigned different targets to variants, including portable/wireless uses and performance-oriented CPU, GPU, and FPGA uses. |
| What production status is documented? | The cited 32 nm announcement is a development milestone. TSMC announced 28 nm volume production in October 2011, naming 28HP, 28HPL, and 28LP as in volume production. |
| Which is faster, lower-power, cheaper, or denser? | Not established as a universal comparison. The releases cover different variants, dates, application targets, and metrics, with no matched independent 28 nm-versus-32 nm comparison. |
A process name is not enough to infer a chip’s clock speed, power use, cost, yield, or density. The releases describe multiple process options and company-stated targets; performance depends on the specific process variant and chip design. The figures above should not be used as a head-to-head ranking.
What does “nm” mean here—and what does it not tell you?
In “28 nm” and “32 nm,” nm is part of the foundry process-generation name. It does not, by itself, specify a retail chip, give a complete description of its transistor design, or predict real-world performance. For context, TSMC says its logic technology used planar structures until FinFET production began at 16 nm in 2014. That history does not mean every earlier process variant had identical transistor options. TSMC’s research summary also describes 28 nm high-k/metal-gate CMOS SoC technology aimed at high-performance mobile applications. TSMC’s logic-technology overview provides the company’s account of that progression.
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What chips use TSMC 28 nm?
The announcements establish application categories and customer-design milestones, not a reliable customer-by-customer list of products. TSMC’s 2011 count of more than 80 tape-outs does not name the chips, and a process milestone alone cannot show which retail products used a particular variant. Without model-specific evidence, it would be misleading to assign a named consumer chip to 28HP, 28HPL, 28LP, or 28HPM.
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