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“TSMC 3D packages” usually means TSMC 3DFabric, a portfolio of technologies for stacking silicon dies and integrating them into advanced packages. It is not one package type: SoIC stacks dies vertically at the silicon level, while CoWoS and InFO are backend packaging families with different integration approaches.

What does TSMC 3DFabric include?

TSMC describes 3DFabric as an umbrella portfolio spanning wafer-level, front-end stacking and backend packaging technologies. Its principal families include TSMC-SoIC, CoWoS and InFO. Together, they give designers different ways to combine logic, memory and other dies into a system.

The word “3D” in the portfolio name should not be taken to mean that every 3DFabric package stacks dies vertically. The portfolio includes vertical stacking, 2.5D integration and fan-out packaging.

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How SoIC, CoWoS and InFO differ

Technology Integration approach Typical role
TSMC-SoIC Wafer-level 3D stacking using chip-on-wafer (CoW) or wafer-on-wafer (WoW) schemes Vertically integrates similar or different dies at the silicon level
CoWoS 2.5D advanced packaging Brings multiple SoCs and high-bandwidth memory stacks together in a package; TSMC identifies CoWoS-S, CoWoS-R and CoWoS-L variants
InFO Integrated fan-out packaging Backend packaging family with derivatives for different integration needs, including InFO-oS for HPC-oriented applications

These are complementary approaches rather than interchangeable names for the same package. TSMC presents them as options for design-specific system integration, not as a universal performance ranking. See TSMC’s descriptions of SoIC, CoWoS and InFO.

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How the technologies can work together

A 3D die stack and the package around it are separate integration stages. TSMC says SoIC-integrated chips can subsequently be assembled into conventional packages or combined with further 3DFabric services such as CoWoS. A design can therefore use vertical stacking within a chip assembly and a different packaging technology around that assembly.

Why use one of these approaches?

TSMC associates 3DFabric with applications such as high-performance computing (HPC), AI, cloud and data-center systems, networking and mobile devices. Depending on the design, integrating multiple dies can help address bandwidth, latency, power, footprint, design flexibility or reuse of chiplets. Those are design goals and tradeoffs, not guaranteed outcomes for every implementation.

The relevant choice depends on what must be integrated and how. A design team may weigh vertical die stacking against side-by-side integration, memory placement, die-to-die interconnect requirements, package footprint, power and signal integrity, and manufacturing constraints. TSMC’s HPC platform information describes application context; it does not establish one approach as best for every product.

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  • Superior Stability For Precise Work: Designed for, low-friction movement, the guideway helps reduce during sliding and supports stable. The 15mm guideway width, 40mm guideway hole spacing, and 32 x 42.1mm slider size provide defined installation for users working on CNC equipment, 3D printers, semiconductor manufacturing equipment, and linear motio
  • Lightweight And Portable Design: The compact MGN15 configuration is designed for small linear motion machinery and equipment where controlled movement is needed within a defined installation area. With a 15mm width and 350mm length, it can be into suitable mechanical assemblies, supporting practical installation for equipment builders, technicians,
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What to remember about the terminology

  • 3DFabric is TSMC’s portfolio name.
  • SoIC is its wafer-level vertical stacking platform.
  • CoWoS is its 2.5D package technology.
  • InFO is its integrated fan-out packaging family.

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