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Custom silicon can make sense when a company has enough production volume, a sufficiently distinctive workload, or demanding efficiency targets to justify engineering and manufacturing costs. The price varies enormously: a 2023 estimate put a complex 5nm-class SoC design above $540 million, while the same year TechInsights’ Dan Hutchenson said the average chip design cost less than $4 million in 2022. Those figures describe very different scopes, not competing quotes for the same project.
Why companies consider designing their own chips
Off-the-shelf processors let a company avoid much of the cost and risk of chip development, but they also impose someone else’s architecture, performance profile and roadmap. A custom ASIC or SoC can be tailored to a particular workload—for example, an AI accelerator or image processor—and may offer lower power use, better performance per dollar, or functionality a general-purpose chip does not provide.
That advantage matters most when the chip will ship in large numbers or when its capabilities help distinguish the product from competitors. Sondrel’s Curren put the competitive issue simply: “The problem with off-the-shelf is that rivals can buy exactly the same chips.” A custom design does not guarantee a winning product, though. It exchanges some of the flexibility and lower upfront commitment of buying standard silicon for development expense, schedule risk and responsibility for a design that must work at scale.
In a July 2023 EE Times report, Arm vice president Dermot O’Driscoll described custom SoC projects as a broad trend across industries, driven by pressure for more compute and efficiency. The report pointed to interest from hyperscalers, AI startups, automotive and mobile companies, and cited potential applications in 5G, healthcare and server systems. That is an adoption thesis from 2023, not evidence that every company or workload benefits from a custom chip.
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What does custom chip design cost?
There is no single representative price. Design cost depends on the chip’s complexity, process node, engineering scope and what is counted in the program. A focused block or image processor is not comparable to a platform effort involving several chips and extensive software. The estimates below come from different speakers and describe different scopes; they should be read as context, not as a standardized price list.
| Figure | Scope and attribution | How to interpret it |
|---|---|---|
| More than $540 million | International Business Strategies (IBS), cited in a 2023 Semiconductor Industry Association context, for designing a complex 5nm-class SoC. | A high-end estimate for a complex design, not the cost of every custom chip. |
| More than 80% higher than at 7nm-class | IBS, cited in the same 2023 context, comparing a complex 5nm-class SoC design with a 7nm-class design. | The comparison illustrates how process-node choice can affect design expense; it is not a universal node-to-node pricing rule. |
| $80 million to $200 million | An estimate for relatively sophisticated AI SoCs attributed to Freund in EE Times in 2023. | A range for sophisticated AI SoCs, not a quote for a small accelerator or a complete multi-chip platform. |
| More than $20 million for masks; often $100 million to $200 million for a whole AI-chip program | Sudhir Mallya of Alphawave Semi, quoted by EE Times in 2023. | The mask figure is one component; the broader program estimate indicates that the full effort can extend well beyond design alone. |
| Less than $4 million average design cost in 2022 | Dan Hutchenson of TechInsights, quoted in EE Times in 2023, said average cost per design had risen 6% annually over the preceding five years. | This is an average across chip designs as reported, not an estimate for a complex AI SoC or a company’s full custom-silicon program. |
The spread is not a contradiction: an industry-wide average can include many designs with narrower scope, while an advanced SoC estimate may include substantial engineering complexity. A platform program can also bundle software and multiple chips, making it far more expensive than a focused accelerator or image processor. Before comparing any estimates, establish whether they cover engineering alone, masks and fabrication preparation, software, multiple components, or a complete program.
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When can the economics work?
A custom chip has substantial upfront costs, so its business case depends on what it saves or enables over the product’s life. The central question is whether expected gains—such as lower per-unit cost, improved efficiency or unique functionality—can repay development and production commitments. High volume can spread fixed costs across more units; strong differentiation can justify the investment even if the chip does not have the lowest unit cost.
- Volume: More units can help amortize fixed development expense, but only if demand is real and sustained enough to use the design.
- Workload fit: A narrow, repeated task may benefit from specialized hardware more than a workload that changes frequently or needs broad general-purpose capability.
- Efficiency and product value: Savings in power, performance or system cost matter only if they translate into a measurable benefit for the product or its users.
- Differentiation: Unique capabilities can support a custom design where competitors can otherwise buy the same off-the-shelf chips.
- Risk and timing: Engineering delays, manufacturing constraints or a product roadmap that changes before launch can erode the expected return.
Custom silicon is therefore not automatically cheaper, faster or better. It is most compelling when a company can state what the chip must do, how many units it expects to deploy, and how the resulting advantage will be worth the upfront commitment.
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In-house, hybrid or turnkey design?
Companies can keep the work inside their own engineering organization, divide it with a specialist, or contract a design-to-order firm to manage most of the implementation. The right boundary depends on existing expertise, desired control and how much responsibility the company is prepared to retain.
| Approach | Upfront engineering cost and talent | Architecture, IP and software | Volume, savings and differentiation | Schedule, node and supply chain |
|---|---|---|---|---|
| In-house | Requires building or maintaining a substantial team and access to specialized design skills; the company carries the direct engineering burden. | Offers the greatest direct control over architecture and internal IP. The company also owns more of the software and integration burden. | Best suited to organizations expecting enough volume or strategic differentiation to justify sustained investment. | The company bears more schedule and execution responsibility, including coordinating process-node choices and supply-chain work. |
| Hybrid | Shares the work between the customer’s team and an ASIC partner, limiting the need to staff every specialty internally. | The customer can specify architecture and contribute its IP while relying on the vendor for implementation. Software responsibilities must be agreed between the parties. | Can preserve important product differentiation without recreating a full chip-design organization. | Provides a division of execution work; the contract should make clear who handles manufacturing coordination, schedule and supply-chain tasks. |
| Turnkey design-to-order | A specialist firm assembles the required design team and manages much of the end-to-end work, reducing the need for an internal chip organization. | The provider can tailor an ASIC or SoC to the customer’s workload and incorporate customer IP. The customer still needs to define requirements and align on software and ownership. | Can enable custom silicon for a company without a large internal team, but does not remove the need for a credible volume or differentiation case. | Firms such as Sondrel offer to manage parts of the supply chain; the exact division of responsibility depends on the engagement. |
The labels do not determine the contract. In particular, “turnkey” should not be taken to mean that the customer has no engineering role or that every software, manufacturing and supply-chain obligation transfers to the provider. Define the deliverables, IP rights, software scope, production responsibilities and decision authority before choosing a model.
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Consumer-electronics companies commonly use a hybrid arrangement, according to the 2023 report: they specify the architecture and rely on an ASIC vendor for implementation and manufacturing. Synopsys’ John Koeter observed that it is “relatively rare for a consumer [electronics] company to do a full turnkey SoC design.” That observation is about consumer electronics, not a rule for every industry.
Can AI tools make chip design affordable to smaller companies?
AI-enabled electronic design automation (EDA) tools can help engineers explore more design options and automate parts of verification, layout and optimization. The 2023 report highlighted Synopsys.ai and DSO.ai for tasks including verification, benchmark generation, coverage and layout optimization, and described Ansys and Cadence as adding related AI capabilities. These capabilities may shorten iteration or let a team evaluate more alternatives, but they do not eliminate the need for experienced chip engineers or make advanced manufacturing inexpensive.
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Synopsys announced in May 2023 that DSO.ai had been used to place and route more than 200 chip designs in about two years. That is a vendor-reported deployment figure, not a controlled measurement of cost savings, schedule reductions or results available to every customer. It supports the point that AI-assisted tools were being used on real designs by that date; it does not establish that a small company can build a complex chip without specialist expertise.
For a smaller company, the practical accessibility gains are narrower but meaningful: AI-assisted tools may reduce some iteration burden, while a design partner can supply specialists and coordinate implementation. The company still needs a clear workload, product requirements, engineering oversight and a plan for software and production.
How to decide whether to proceed
- Define the workload. Identify the repeated computation or function that standard chips handle poorly, and specify the performance, power and functionality targets that matter to the product.
- Estimate demand and value. Forecast likely unit volume and product lifetime, then identify how a custom design could reduce unit cost, improve efficiency or create capabilities competitors cannot readily match.
- Set the scope before comparing costs. Determine whether the project is a focused accelerator, an SoC, or a broader platform with software and multiple chips. Ask estimates to state what engineering and program expenses they include.
- Choose the operating model. Decide which architecture and IP decisions must remain internal and which implementation, verification, manufacturing and supply-chain tasks can be handled by a partner.
- Evaluate node and schedule trade-offs. Treat process-node requirements as a cost and execution decision, not simply a specification target. Confirm that the selected approach fits the intended product schedule.
- Test the business case against failure scenarios. Revisit the economics if volume is lower than forecast, the workload changes, the design slips, or the expected efficiency and differentiation do not materialize.
If a standard chip already meets the product’s needs, or demand is too uncertain to support the upfront commitment, buying off-the-shelf silicon may be the more sensible choice. If the workload is stable, the payoff is substantial and the company can manage the design and production risks—internally or with a capable partner—custom silicon becomes a credible option.
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