iTechGuides is reader-supported. When you buy through links on our site, we may earn an affiliate commission. As an Amazon Associate I earn from qualifying purchases. Learn more
A custom ASIC or SoC becomes economically viable when its discounted lifetime savings and other measurable benefits exceed its added design, production, qualification, and schedule costs. There is no universal volume threshold: a high-volume product can still be a poor candidate if the per-unit savings are small, while a complex design may justify custom silicon at lower volume if it replaces costly components or delivers valuable system benefits.
Start with the break-even calculation
For a quick screen, divide the custom option’s incremental fixed cost by its net savings per shipped unit:
Break-even lifetime units ≈ incremental fixed cost ÷ net savings per unit.
The Tool Desk
Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Use net savings, not an assumed difference between chip prices. Compare the cost of the existing implementation—including the relevant components, assembly, test, and system costs—with the ASIC’s silicon, package, production test, royalties, and any changes to assembly or the system. Subtract the custom option’s recurring costs from the baseline’s recurring costs to find the savings per unit. If the ASIC costs more per unit, the simple calculation does not produce a positive break-even volume.
#1 Best Overall
- Air Cooling & Low Noise Operation – This air-cooled ASIC development board runs at 50dB, maintaining stable temperature during long testing sessions.
- 4x BM1370 Chips – Equipped with 4 dedicated BM1370 ASIC chips to deliver steady processing capacity, ideal for chip testing, algorithm verification and embedded system debugging.
- Open Source Firmware – Fully open-source firmware with public code access. Ethernet supports remote monitoring and setting adjustment through a web browser.
- Compact & Lightweight Design – Net weight only 0.45kg, with 10×14×18cm dimensions, perfect for placement on lab benches and workstations.
- Built-in IPS Display – Integrated IPS screen shows real-time operating data for convenient setup and daily testing.
This is a screening equation, not a full investment decision. A more complete comparison discounts the cash flows for each technically feasible route to a common date, then compares total lifecycle cost or net present value. Include when development spending occurs, when production starts, the expected product life, annual demand and ramp, and the relevant discount rate. If options have different schedules, model dated cash flows rather than treating all units and costs as if they occur at once.
Which costs and benefits belong in the model?
Build a separate estimate for each credible implementation. Count only incremental costs: for example, architecture or RTL work that every route would require should not be charged only to the ASIC. Conversely, include custom-silicon costs that a board-level or FPGA design avoids.
Rank #2
- The Coral Dev Board Mini is a single-board computer that enables you to quickly prototype and deploy an embedded system with on-device ML inferencing.
- The board includes the Edge TPU coprocessor, which is a small ASIC designed by Google that accelerates TensorFlow Lite models in a power efficient manner. It's capable of performing 4 trillion operations (tera-operations) per second (tops), using 0.5 watts for each tops (2 tops per watt).
- Provides a complete system: a single-board computer with SoC + ML + wireless connectivity, all on the board running a derivative of Debian Linux we call Mendel, so you can run your favorite Linux tools with this board.
- Supports TensorFlow Lite: no need to build models from the ground up. Tensorflow Lite models can be compiled to run on the Edge TPU.
- Supports AutoML Vision Edge: easily build and deploy fast, high-accuracy custom image classification models to your device..MediaTek 8167s SoC (Quad-core Arm Cortex-A35).2 GB LPDDR3 and 8 GB eMMC memory
- Fixed development and launch costs: design and verification, third-party IP, EDA tools, physical design, masks and tape-out, prototypes, test development, productization, and qualification. Separate shared work from costs unique to a route.
- Recurring costs: component or device purchase, die area, package, production testing, royalties, assembly, and any relevant system-level costs. Silicon area, packaging, and testing are among the factors that drive ASIC unit cost, as ICsense explains.
- Schedule and lifecycle effects: time to prototypes and production, sales delayed or lost during a transition, product lifespan, redesign or respin risk, and the effort needed to maintain the design as requirements change.
- Value beyond purchase cost: power, performance, footprint, integration, and differentiated functionality. Quantify these benefits separately when possible; do not assume that a custom chip automatically delivers them.
- Who receives the savings: an OEM may capture lower board and supplier costs, while a semiconductor vendor may calculate return from chip sales. The same design can therefore have different economics for different participants in the supply chain, a distinction discussed in ARM’s 2015 Custom ASIC Economics white paper.
Do not count the same benefit twice. If a smaller board reduces assembly cost, for example, include that reduction either in the per-unit system savings or as a separately modeled benefit—not both. Treat volume, savings, schedule, NRE, and redesign risk as uncertain inputs. A range or sensitivity analysis is more useful than a single precise crossover when the estimates are not firm.
Compare technically suitable routes, not just chip prices
Technical feasibility comes first: a platform that cannot meet the product’s requirements is not a genuine economic alternative. Among feasible routes, compare incremental fixed cost, recurring system cost, schedule, flexibility, qualification, expected volume, and product life.
| Route | Economic attraction | Important trade-off |
|---|---|---|
| Existing discrete or board-level design | Avoids custom-silicon NRE and retains established components. | May keep higher component, board, assembly, or system costs; model the actual design baseline. |
| FPGA or programmable logic | Flexibility and simpler changes can be valuable at lower volumes or while requirements remain uncertain. | Per-unit costs may remain higher. A later FPGA-to-ASIC redesign adds work and schedule risk. A 2008 SEC-filed Form 10-K describes this general flexibility and development-cycle trade-off: SEC filing. |
| Structured ASIC | Can offer a middle ground in NRE and implementation time where a suitable platform exists. | Available gates, memory, IP, package, and performance constrain fit; unit cost may be higher than a standard-cell ASIC. |
| Standard-cell ASIC | Custom layout can reduce die area and recurring unit cost when the savings justify the investment. | Higher NRE and a longer implementation schedule make lifetime volume and launch timing central to the case. |
Structured ASIC constraints and the schedule and NRE trade-offs among these routes are illustrated in EDN’s comparative case study. Its example is useful for understanding the model, not for selecting a current platform or price.
How to interpret published crossover figures
Published numbers show how a particular set of assumptions can move the answer; they are not interchangeable market quotes. Keep each figure attached to its date, project, and scope.
Rank #4
- NerdMiner V2 Preloaded Bitcoin Lottery Miner Comes with NerdMiner V2 preloaded for Bitcoin lottery-style solo mining. Connect to 2.4 GHz Wi-Fi and complete setup to use it as a compact desktop BTC lottery miner. Typical performance is about 350 KH/s and may vary by settings and network conditions.
- ESP32-WROOM-32E Module Inside Built with the ESP32-WROOM-32E wireless module, supporting 2.4 GHz Wi-Fi, Bluetooth and BLE. It is also a programmable ESP32 development board for IoT, smart home, sensor display, dashboard and DIY electronics projects.
- 2.8 Inch 240x320 Touch Display Features a 2.8-inch 240 x 320 TFT LCD touch screen with resistive touch control. Suitable for status display, menu control, graphical interface, monitoring dashboard and custom touchscreen applications.
- Reprogrammable Development Board NerdMiner V2 is only the preloaded application. Users can erase or replace it with compatible ESP32 programs using Arduino IDE, PlatformIO, ESP-IDF or MicroPython for custom development projects.
- Complete Desktop Kit Includes the ESP32-2432S028R-PLUS touch screen development board, 3D-printed protective case and USB Type-C data cable. MicroSD card, battery, touch stylus, sensors and expansion modules are not included.
| Published example | What it shows—and what it does not |
|---|---|
| “Rule of 50”: S3 Group’s Donnacha O’Riordan gave the example of saving $50 in BOM cost on a product shipping 50,000 units per year. ARM’s 2015 white paper reports that this could justify a custom ASIC, with an approximate $2.5 million NRE estimate. | The multiplication gives $2.5 million in gross annual BOM savings before ASIC recurring costs and other factors. ARM says the estimate covers work from a blank sheet through a tested, packaged IC for prototype-board construction. It is a practitioner heuristic, not a universal NRE quote or break-even rule. ARM white paper (2015). |
| 12–18 months to ROI crossover: ARM’s 2015 white paper presents this as typical in the board-to-custom-ASIC context it discusses. | It is a historical illustration, not a schedule promise for a new project. Development time, ramp, product life, costs, and the definition of ROI all affect an actual crossover. ARM white paper (2015). |
| 40,000–45,000 units per month: An Electronic Design case study reported this demand alongside $1 million in ASIC design and mask NRE, $392,000 in automotive AEC-Q100/productization costs, and a $1.46 ASIC unit price. | These figures belong to the reported 130-nm project, which used flash, analog metals, and thick oxide; the article was published approximately in 2019. They are not current pricing or a general threshold. Electronic Design case article. |
| $0.10 to several dollars per chip: ICsense gives this broad unit-price range based on supplier experience; its page was accessed in 2026. | The supplier says price varies with application, technology, die size, package, testing, and volume. Treat the range as context, not a budget quote. ICsense unit-price explanation. |
| Historical annual-volume bands: EDN’s approximately 2005 model put FPGA below 1,500 parts, structured ASIC above 2,000 and below 8,500, and standard-cell ASIC above 8,500. | The illustrative model assumed 250,000 gates, 200 MHz, a 250-pin BGA, and a three-to-five-year ASIC life; it listed NRE/unit costs of $0/$80 for FPGA, $200,000/$40 for structured ASIC, and $800,000/$12 for standard-cell ASIC. These old assumptions and prices are not transferable recommendations. EDN case study. |
| 2,200 units per year: EDN’s complex-design example found standard-cell ASIC to be the lowest-cost option at this annual volume under its study assumptions. | The case involved five million gates, 3-Mbit internal memory, and high-speed SERDES. It demonstrates how complexity and unit savings can shift the crossover; it does not establish a general 2,200-unit threshold. EDN case study. |
A practical decision process
- Confirm technical fit. Define the requirements for performance, power, interfaces, memory, package, reliability, and product life. Remove any implementation that cannot credibly meet them.
- Set the baseline. Estimate the current board or system cost per unit, including the components the custom chip would replace and any relevant assembly, test, and system effects.
- Request scoped estimates for each credible route. Break out engineering and IP, masks, prototypes, silicon, package, test, qualification, production timing, and unit cost. A useful estimate needs the actual architecture, process, package, test plan, qualification needs, and geography.
- Forecast the units you can ship. Use annual demand and ramp over the product’s realistic remaining life, not addressable-market size or a single peak-volume year.
- Calculate and stress-test lifecycle economics. Discount dated costs and benefits to a common baseline. Test conservative, expected, and upside volume alongside delayed production, lower savings, higher NRE, and one redesign or respin.
- Make the decision on total value. Check whether the economic case still holds when uncertain inputs move, and include only defensible power, performance, footprint, or integration value. Report a crossover range when estimates are uncertain.
The evidence supports no universal current NRE, yield, or annual-volume threshold. The right answer for a particular product depends on a technical feasibility review and current, project-specific estimates from the design, foundry, package, and test participants. ARM’s discussion of proprietary, complexity-dependent economics and the dated assumptions in the EDN examples are reasons to treat simple cutoffs as illustrations rather than forecasts.
Quick wins for a faster PC:
Scan for outdated or missing drivers - takes under a minuteDriver Scan →Repair Windows errors before they cause bigger problemsFix Now →Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
