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SiFive’s XM Series is licensable AI-accelerator IP for semiconductor companies, not a retail accelerator card or an off-the-shelf chip. For XM Series Gen 2, SiFive specifies 16 TOPS (INT8) per GHz per cluster and 8 TFLOPS (BF16) per GHz per cluster. It also claims 1 TB/s of sustained bandwidth per cluster. These are vendor specifications, not independent benchmark results; the available sources do not establish power draw or energy per inference, so they cannot verify that the design is energy-efficient in measured use.
What is SiFive’s XM Series?
XM Series is part of SiFive Intelligence, a portfolio of licensable processor IP that semiconductor companies can integrate into their own system designs. It is not a finished accelerator product that buyers can install in a PC or server. SiFive positions XM for AI workloads across edge, automotive, consumer-device, and data-center markets, with Gen 2 described as heavily tuned for large language models (LLMs). Those are intended markets and product positioning, not evidence of customer deployments.
SiFive announced its second-generation Intelligence family on September 8, 2025, including XM Gen 2. The company said the five announced products were available for licensing immediately and forecast first silicon in Q2 2026. That date was a forecast at announcement time; the cited material does not confirm whether silicon subsequently shipped. SiFive’s 2025 announcement
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsWhat does 16 TOPS mean for an XM cluster?
On its current XM Series product page, SiFive specifies 16 TOPS (INT8) per GHz per cluster and 8 TFLOPS (BF16) per GHz per cluster. The precision and clock-rate qualifiers matter: these figures are normalized per GHz, not an absolute peak for a cluster running at an unspecified clock. They should not be read as a measured application result. SiFive XM Series product page
#1 Best Overall
- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
- TOPS means tera operations per second; here the stated figure is specifically for INT8 operations.
- TFLOPS means tera floating-point operations per second; the stated figure is specifically for BF16 operations.
- Per GHz per cluster expresses throughput relative to clock frequency for one cluster. It is not a stated absolute chip-wide number, and the source does not provide a specific operating clock to convert it into one.
SiFive also lists 1 TB/s sustained bandwidth per XM Series cluster. That is a vendor-stated bandwidth specification, not proof that a particular model or application will achieve a corresponding throughput. The original launch materials also reported these throughput and bandwidth specifications. SiFive’s XM Series announcement
How does XM Gen 2 combine its cores and matrix engine?
SiFive says XM Gen 2 integrates a scalable matrix engine with four second-generation X300 cores per cluster. Between one and four of those X-cores can act as accelerator control units for the matrix engine. The design also uses the X-cores for other work, including activation functions. SiFive describes the architecture as a “Fat Outer Product” matrix engine, tightly integrated with the X-cores and fused with vector units. SiFive XM Series product page
Rank #2
- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
In SiFive’s description, the scalar unit fetches new matrix instructions, source data comes from vector registers, and results are written to matrix accumulators. The intended effect is close coordination between scalar control, vector operations, and matrix computation; the published figures alone do not show how quickly a complete application runs.
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SiFive describes two memory paths for the four internal X-cores:
Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
- Shared cached ports: these support coherence among the four X-cores.
- Dedicated high-bandwidth uncached port: each X-core has its own such port.
SiFive says the host processor may be RISC-V, x86, or Arm, or there may be no host. These options describe integration flexibility for a customer-designed system; they do not establish that every configuration is available in a particular product or that memory bandwidth translates directly into application performance. SiFive XM Series product page
Does “energy-efficient” mean XM has proven low power?
No independent power draw, energy-per-inference result, or equivalent-condition comparison with another accelerator is established in the cited material. SiFive describes XM as high-performance-per-watt and presents it as efficient, but that remains vendor positioning without published measurements here. A throughput figure, even alongside a bandwidth specification, is not enough to calculate energy use.
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
To assess efficiency for a real design, a buyer would need measurements under comparable conditions, including the target model and workload, precision, throughput, latency, system configuration, and power measurement boundary. Energy per inference or throughput per watt would be more informative than peak throughput alone. No such XM results are provided in the sources cited here.
What should a buyer compare before licensing AI accelerator IP?
XM’s published figures are useful specifications, but they do not support a ranking against competing IP. A meaningful comparison should align the evidence across several dimensions:
Best Value
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
- Throughput: compare the same precision and clock basis, and distinguish vendor peak specifications from measured application performance.
- Workload results: use the same model, input sizes, batch conditions, and performance targets.
- Efficiency: compare measured energy per inference or throughput per watt under stated system and measurement conditions.
- Memory behavior: examine bandwidth, data movement, caching, and how the accelerator connects to its host and memory.
- Implementation: establish area, process assumptions, software support, and licensing and access terms for the intended design.
SiFive founder and chief architect Krste Asanovic wrote in a September 24, 2024 blog post that “a flexible and scalable hardware solution is needed to maximize AI software investment.” That statement describes the rationale for flexibility; it is not an independent performance or efficiency result. SiFive’s 2024 blog post
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