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Menta eFPGA is programmable-logic IP embedded inside an ASIC or SoC. Its proposed advantage for aerospace and defense is post-fabrication adaptability: selected hardware behavior can be changed after the main chip is manufactured, potentially extending a platform’s usefulness as missions, algorithms, protocols and security requirements evolve. Whether it is the right choice depends on integration effort, configuration security, radiation evidence, qualification plans and lifecycle economics—not on reconfigurability alone.
What Menta eFPGA is
An embedded FPGA (eFPGA) is programmable logic implemented inside a custom ASIC or SoC rather than a separate FPGA connected on a circuit board. Menta describes its cores as third-party standard-cell IP that can be delivered as soft RTL or hard GDSII, with industrial-grade or radiation-hardened implementation options selected during physical implementation. Its product overview says standard-cell construction is intended to support compatibility across production nodes and technologies: Menta eFPGA product overview.
Menta’s Origami Programmer supports Verilog, SystemVerilog and VHDL workflows and can operate standalone or within a customer’s design flow, according to the company’s March 2025 Launch Pad announcement: Launch Pad announcement. The programmable region is still part of a larger fixed ASIC design; it does not make every block of that ASIC freely reconfigurable.
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1. Reconfiguration can extend a long service life
Menta’s EE Times partner article argues that aerospace and defense equipment may remain in service for 10–30 years, and that an eFPGA can accommodate post-deployment bug fixes, algorithm changes and new protocols without respinning the entire ASIC. That 10–30-year range is the article’s contextual statement, not a universal service-life statistic: Menta-authored EE Times partner article.
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The practical benefit is greatest when the functions most likely to change are deliberately placed in the programmable fabric and the product has a controlled field-update path. An eFPGA cannot repair an error in an unrelated fixed-function block, add resources that were not designed into the chip, or bypass a system’s maintenance and certification process.
2. Configurable logic can support security and cryptographic agility
Menta argues that programmable logic allows security functions and cryptographic implementations to be updated as threats and requirements change. This can be valuable where a platform must replace an algorithm, alter a protocol or respond to a discovered implementation weakness without replacing the main silicon.
Claims about bitstream obfuscation, erase behavior, tamper resistance or attack resilience are architecture-specific vendor claims, not automatic properties of every eFPGA. A security review should examine key storage, bitstream authentication and encryption, rollback prevention, debug access, update authorization, fault response and the separation between programmable and fixed logic. The Menta article’s security case is presented here as the vendor’s position, not independent validation: EE Times partner article.
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3. One ASIC can be tailored to missions or regions
Menta says a common ASIC design can be configured for different mission profiles, customers or regional requirements. A programmable block may hold variant interfaces, data-processing pipelines or control logic while the surrounding chip remains common.
This approach can reduce the number of mask sets and board-level variants a program must manage, but configuration control becomes part of product configuration management. Reconfiguration does not by itself resolve export controls, country-specific approvals, classified-data handling or other regulatory obligations. Those requirements still apply to the complete system and to every configuration delivered.
4. Integration may improve SWaP-C, data movement and latency
Menta’s comparison with a discrete FPGA emphasizes on-chip integration. Eliminating a separate FPGA can reduce board area and external communication, and a shorter on-chip path may reduce some data-movement overhead. The same article acknowledges that a discrete FPGA can offer a shorter initial design schedule in some projects: vendor comparison in EE Times.
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Those are design hypotheses, not universal measurements. A fair architecture study should compare the complete implementation:
| Decision axis | Embedded eFPGA | Discrete FPGA | Fixed-function ASIC logic |
|---|---|---|---|
| Physical integration | Programmable fabric is inside the ASIC or SoC. | Requires a separate package, board area and interconnect. | Highest functional integration, but behavior is fixed after fabrication. |
| Post-fabrication updates | Possible for functions mapped into the fabric, subject to configuration controls. | Usually supported, with an external device and its own supply and lifecycle. | Generally requires a silicon revision for hardware changes. |
| Power, area and communication | Potentially avoids some chip-to-chip I/O, but depends on fabric size, routing and operating point. | Includes device, package, board, I/O and power overhead. | Can be efficient for stable, well-defined functions. |
| Initial schedule | Requires ASIC integration, physical implementation and verification of the eFPGA. | May shorten early hardware development for some designs, as Menta’s comparison notes. | Requires a fixed-function architecture and full ASIC implementation. |
| Lifecycle supply exposure | One ASIC may cover more variants, but the ASIC itself still needs long-term supply planning. | Depends on continued availability and qualification of the external FPGA. | Depends on the fixed ASIC’s production and revision plan. |
| Qualification evidence | Must cover the selected process, cell library, implementation and environment. | Must cover the FPGA device, board and operating environment. | Must cover the chosen ASIC process and fixed design. |
Power, unit cost, latency, schedule and total cost therefore require project-specific models and measurements rather than a blanket winner.
5. Standard-cell and radiation options may help harsh-environment designs
Menta describes standard-cell implementation and radiation-hardened options for its eFPGA IP. That gives a design team a path to select an implementation appropriate to its process and environment: Menta product overview.
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It is not a blanket radiation-hard guarantee. Before accepting the IP for an A&D mission, request evidence for the exact process and library, total-ionizing-dose limits, single-event upset and transient behavior, latch-up susceptibility, redundancy or scrubbing strategy, timing margins, packaging and temperature range. The available Menta material does not provide independent dose, upset-rate or qualification results. A vendor architecture presentation, such as the FPL 2025 material, should be treated as technical background rather than independent qualification evidence: FPL 2025 presentation.
6. Launch Pad can lower the barrier to a prototype
Menta announced Launch Pad on March 18, 2025 as a discounted test-chip licensing program for eligible new defense and aerospace customers. That announcement described eFPGA sizes from 100 to 10,000 LUTs, discounts of up to 90% off standard licensing fees and soft-RTL delivery in as little as 14 days. These are dated, vendor-published offer terms—not an independent service-level commitment—and current eligibility, pricing, availability and delivery must be confirmed with Menta: Launch Pad terms.
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7. An implementation ecosystem can fill specialist gaps
Menta’s A&D article and Launch Pad announcement describe an ecosystem of design-house and specialist IP partners. Such partners may help with physical implementation, verification, security architecture or domain-specific integration. Scope, geography, current availability and responsibility boundaries should be confirmed with Menta and each named organization before a program relies on them: EE Times partner discussion.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Questions to resolve before selecting an eFPGA
- Define the change budget. List which algorithms, protocols, interfaces and control functions may change during the platform’s life. Size the fabric, memory, DSP and routing resources against those functions, including growth margin.
- Choose the implementation form. Determine whether the project needs soft RTL for flexibility in the customer flow or hard GDSII for a more fixed physical implementation. Confirm supported process nodes, standard-cell libraries, clocks, resets, scan insertion and physical-design requirements.
- Design the configuration security chain. Specify who can generate, sign, approve, load, revoke and recover a bitstream. Review key management, anti-rollback controls, debug lockdown, fault handling and secure erase with the system security authority.
- Build an environmental qualification plan. Set radiation, temperature, vibration, reliability and mission-duration requirements, then require data for the exact implementation rather than relying on a generic “radiation-hardened” label.
- Model the complete SWaP-C case. Compare eFPGA integration with a discrete FPGA and fixed logic using measured or vendor-supported estimates for power, board area, I/O, latency, engineering labor, verification, tooling, package effects, recurring cost and nonrecurring cost.
- Verify update behavior. Test interrupted updates, invalid images, rollback, recovery, partial reconfiguration assumptions, reset sequencing and operation during configuration. Include the field or depot process, not only RTL simulation.
- Plan lifecycle supply and configuration management. Establish how the ASIC, programming tools, IP licenses, masks, test collateral and approved bitstreams will be maintained for the expected service period.
Do not confuse the eFPGA IP with Menta’s MFC chiplet
Menta’s separate MFC eFPGA chiplet page describes a specific 22 nm configuration with 50,000 logic cells, 96 DSPs, 2.36 Mbits of embedded RAM, and UCIe and QSPI connectivity: MFC eFPGA chiplet page. Those figures describe that chiplet family and should not be substituted for the size or capability of the eFPGA soft IP discussed in the A&D article.
Menta’s July 2025 Renesas announcement is an example of a commercial license for Renesas’s ForgeFPGA product line. It demonstrates a licensing relationship, not qualification or suitability for a particular aerospace or defense design: Renesas license announcement.
Bottom line
Menta eFPGA is most compelling when a custom ASIC must remain adaptable after fabrication and the team can place likely-to-change functions inside a securely managed programmable region. Its proposed advantages—long-life updates, cryptographic agility, mission variants, possible SWaP-C gains, harsh-environment implementation options, prototype access and partner support—are vendor arguments. The decision should rest on an architecture-specific comparison and documented security, radiation, verification, supply and qualification evidence.
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