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Sarcina Technology announced patented design methodologies for UCIe-A and UCIe-S on September 9, 2025. The two approaches address different parts of chiplet packaging: UCIe-A focuses on redistribution-layer interposers, while UCIe-S targets organic substrates and HDI printed circuit boards. Sarcina presents them as a combined design and simulation platform for links inside packages and connections that extend across packages and boards.
How do Sarcina’s UCIe-A and UCIe-S methodologies differ?
| Design consideration | UCIe-A | UCIe-S |
|---|---|---|
| Physical medium | RDL interposer | Organic substrate or HDI PCB |
| Routing location and scope | Package-level die-to-die routing at the die edge | Compact multilayer routing at the die edge, with package-to-package and board-level scaling |
| Rate described by Sarcina | 32 GT/s, which the company says is compliant with UCIe 2.0 | 32 GT/s performance reported from 3D HFSS simulations; the company does not identify an independent test report |
| Manufacturing emphasis | Fewer RDL routing layers within manufacturing limits and standardized layouts intended to improve fabrication yield | Routing designed for organic substrates and HDI boards; a comparable layer-count or yield claim is not stated in the cited company materials |
| Intended deployment | Links between dies within a package | Links that can extend to daughter cards, accelerator modules and system baseboards |
How does Sarcina say its UCIe-A interposer design works?
The UCIe-A methodology uses an RDL interposer and arranges routing channels along the die edge, an area sometimes called the “beach front.” Sarcina describes multidimensional routing for data, clock and redundancy signals, with the aim of fitting interconnects into a constrained edge region while limiting crosstalk and preserving signal integrity.
The company’s design approach also seeks to reduce the number of RDL routing layers without exceeding manufacturing limits. Sarcina says it uses standardized RDL layouts to support fabrication yield. These are design goals and company claims; the announcement does not publish an independent yield study or comparative measurement.
What does Sarcina claim for UCIe-S?
For UCIe-S, Sarcina describes low insertion loss and crosstalk in compact multilayer routing on organic substrates and HDI PCBs. It reports 32 GT/s performance based on advanced 3D HFSS simulations, and says communication can operate with silicon transmitter and receiver equalization disabled. According to the company, that could avoid power otherwise used by additional equalization transistor circuits.
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The 32 GT/s result is a simulation claim from Sarcina, not an independently published test result in the materials describing the announcement. The sources do not provide measured hardware results, test conditions or a direct comparison against another implementation, so the figure should not be treated as independently validated product performance.
What systems is the combined platform intended to support?
Sarcina positions UCIe-A and UCIe-S together as a design and simulation platform spanning interposers, package substrates and PCBs. The intended architecture is to partition a monolithic system-on-chip into chiplets, then combine compute, memory, analog and I/O dies that may use different process nodes.
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For co-packaged optics, the company describes combining silicon photonic dies and fiber-array units with compute chiplets. Its target applications include AI acceleration, high-performance computing, data centers, networking and other data-intensive systems. In a separate description of its AI platform, Sarcina reports up to 32 GT/s per lane and up to a 64-bit data interface per module; those are company-stated platform figures, not independent benchmarks.
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Sarcina says it provides custom semiconductor packaging from design and simulation through assembly, testing and production management. Its technology materials list 2.5D silicon-interposer packaging, 3D stacking, multi-chip-module and chiplet implementation, photonic IC packaging, and power-integrity and signal-integrity channel simulations for 32G UCIe-A/S interfaces.
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The engineering challenge is not just choosing a protocol: designers must fit wires into limited package space while managing crosstalk, signal integrity and manufacturing constraints such as available copper layers. Sarcina CEO Larry Zu described wire arrangement under those constraints as a key problem the methodologies are intended to address. The announcement does not give patent numbers or independent validation data for the described designs.
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