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Rapidus and Siemens announced a collaboration to develop design and manufacturing tools for Rapidus’s 2-nm process. Siemens is contributing electronic design automation (EDA) technology and design-flow work, including a planned process design kit (PDK) based on Calibre. Rapidus—not Siemens—is developing and operating the foundry, and its 2027 production date remains a company target rather than a verified commercial result.
What the Rapidus–Siemens 2-nm alliance covers
Announced June 23, 2025, the collaboration is intended to connect chip design tools with Rapidus’s manufacturing process. The companies said they would jointly develop a PDK based on Siemens’s Calibre platform and a reference flow for design, verification, and manufacturing from front end through back end. The flow is intended to support Rapidus’s Rapid and Unified Manufacturing Service (RUMS). Rapidus’s announcement identifies Calibre and Solido as Siemens EDA tools planned for the flow.
A PDK gives chip designers process-specific models, rules, and supporting files needed to develop and check a design for a particular manufacturing process. Calibre is used for physical verification and manufacturing-related checks; the announcement also associates the platform with optimization and reliability assessment. The collaboration is therefore about enabling design work for Rapidus’s process, not about Siemens supplying or running the fab.
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Rapidus describes its approach as manufacturing-for-design: coordinating process and chip-design work early, with the aim of reducing the time customers need to reach tape-out. Siemens and Rapidus have stated goals such as reliability, speed, scalability, and safety, but the announcements do not provide independent performance results establishing those benefits.
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What has Rapidus reported about its 2-nm process?
Rapidus has reported progress on both front-end wafer processing and the design environment. These milestones indicate development activity, but they are not equivalent to proof of commercial manufacturing at competitive yield or volume.
Prototype transistor work and pilot line
On July 18, 2025, Rapidus said it had begun prototyping 2-nm gate-all-around (GAA) transistors at its IIM-1 foundry, with prototype wafers beginning to produce electrical-characteristic data. The company also reported that more than 200 pieces of semiconductor equipment had been connected at IIM-1 in June 2025 and that the facility’s first EUV exposure took place on April 1, 2025, following equipment delivery in December 2024. These are company-reported equipment and process milestones, not commercial output results. Rapidus’s July 2025 update described mass production as a 2027 target.
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PDK and customer prototyping
In an update dated April 11, 2026, Rapidus said its pilot line had begun in April 2025, that it had verified operation of 2-nm GAA transistors on 300-mm wafers, and that it had made a pre-release PDK available to early-adopter customers while establishing customer prototyping conditions. It also said it had achieved its fiscal-year front-end process goals and would continue improving prototype accuracy and implementing yield measures. A pre-release PDK and prototyping environment show that customer-facing development has begun; they do not establish that the process is qualified for high-volume production. Rapidus’s April 2026 process update contains these milestones.
Analysis and packaging capabilities
In a separate April 11, 2026 announcement, Rapidus said its Analysis Center had opened to conduct physical, environmental, chemical, electrical, and reliability analysis. Rapidus Chiplet Solutions also began full-scale operations. The company cited a prototype 600-mm-square redistribution-layer (RDL) interposer panel and said these facilities would support its transition to production in the second half of fiscal year 2027. The panel is a packaging-development milestone, distinct from evidence of volume production of 2-nm logic wafers. Rapidus’s facilities announcement describes the center, chiplet operation, and schedule.
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Will Rapidus make 2-nm chips by 2027?
Rapidus says it is targeting production in 2027; its April 2026 announcement gives the more specific target of the second half of fiscal year 2027. That is the company’s schedule, not an independently validated forecast. The announcements establish neither commercial yield nor planned output capacity, confirmed 2-nm production orders, or independent evidence that the schedule will be met. A prototype transistor, a pilot line, a pre-release PDK, and mass production are different stages, and progress at one stage does not by itself establish readiness for the next.
Rapidus’s design ecosystem has also continued to develop beyond the Siemens relationship. In July 2026, the company announced a separate collaboration with Cadence on agentic-AI support for advanced SoC design. That later agreement is distinct from the Siemens PDK and reference-flow work; Rapidus and Cadence described up to 2X faster design turnaround as a target for their own work, not as a measured result of the Siemens alliance. Rapidus’s Cadence announcement concerns that separate effort.
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- Integrated Antenna: Features PCB trace antenna built directly on-board for immediate testing and development without requiring external antenna components
What the partnership does—and does not—show
- It shows: Rapidus is working with Siemens on process-specific EDA support, a Calibre-based PDK, and a reference flow spanning design through manufacturing.
- It does not show: Siemens is building or operating IIM-1, or that the partnership guarantees yields, production volume, customer orders, or schedule delivery.
- Rapidus’s reported milestones: include GAA transistor prototype work, 300-mm wafer operation verification, pilot-line activity, early-adopter access to a pre-release PDK, and development of analysis and packaging capabilities.
For chip designers, the practical significance is the planned availability of process-specific design support and a customer prototyping environment. For readers assessing Rapidus as a future foundry, the key distinction is between announced development milestones and independently established commercial manufacturing performance.
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