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To change cryptography after an ASIC or SoC has shipped, the device needs programmable hardware inside the security path. Menta’s standard-cell-based embedded FPGA (eFPGA) supplies that programmable region on-chip, allowing a manufacturer to replace or extend cryptographic implementations after fabrication instead of committing every change to a new silicon revision.
That capability matters as standards evolve, vulnerabilities emerge and post-quantum algorithms move into production. It does not remove the need for authenticated bitstreams, key management, validation and certification work, but it gives those controls hardware that can evolve throughout a product’s life.
What crypto agility means in hardware
NIST defines crypto agility as the capabilities needed to replace and adapt cryptographic algorithms for protocols, applications, software, hardware and infrastructure without interrupting a running system, so it remains resilient. In an ASIC or SoC, true agility means more than a software update: the hardware datapath, accelerators, memories, interfaces and boot process must accommodate a new primitive or protocol while preserving device identity and secure-update guarantees.
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Can cryptography be changed after tape-out?
A fixed-function cryptographic block normally cannot be altered after fabrication; changing its algorithm or microarchitecture requires a new silicon version. An embedded FPGA changes that boundary. A signed configuration can replace logic in the eFPGA region after tape-out and, when the surrounding SoC was designed for it, after deployment.
The update path still needs a secure boot chain, authenticated and preferably anti-rollback-protected bitstreams, a recovery image, access control, key rotation and a validation plan. “Programmable” is therefore an enabler of crypto agility, not a substitute for security engineering or certification.
Nine reasons to use Menta eFPGA for crypto agility
1. Replace algorithms after fabrication
Cryptographic requirements often settle after a chip’s architecture is frozen. With fixed IP, a changed algorithm, mode or protocol can trigger a respin. An eFPGA can host a replacement implementation after fabrication, letting the product adapt to revised standards and customer requirements. Menta and Presto Engineering highlighted this post-silicon adaptability in their June 8, 2026 collaboration announcement.
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2. Create a migration path to post-quantum cryptography
NIST identifies cryptographically relevant quantum computers as a reason to migrate from vulnerable public-key schemes. Post-quantum algorithms can have very different arithmetic, memory and bandwidth needs from today’s elliptic-curve or RSA engines. EPI’s description of run-time-reconfigurable post-quantum public-cryptography accelerators on a Menta tile shows how an SoC can reserve a hardware path for that transition instead of assuming one permanent accelerator.
3. Respond when a vulnerability appears
A weak primitive, faulty implementation or newly practical attack can invalidate a deployed design. Reconfigurable logic can carry a replacement implementation while the rest of the product remains in service. The update must be verified and rolled out under the device’s secure-update policy, but avoiding a physical recall or silicon replacement can be decisive for connected, industrial or infrastructure equipment. Menta’s April 22, 2026 announcement about AIST adoption presents evolving threats and post-silicon reconfigurability as central security requirements.
4. Keep FPGA adaptability without an external FPGA link
An external FPGA can provide flexibility, but every transaction crosses a chip-to-chip interface. That adds board traces, pins, protocol logic and another device whose power, timing and supply must be managed. An embedded region keeps the programmable function inside the SoC’s security boundary and can reduce communication exposure, interconnect overhead and latency compared with an external accelerator. The actual gains depend on the SoC floorplan, clocking and workload; the public material does not provide a comparable benchmark.
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5. Manage unsettled protocols and standards
Products designed while a protocol or compliance profile is still changing face a choice between delaying tape-out and accepting a likely redesign. An eFPGA provides a controlled place to implement provisional modes, interoperability changes or final standard revisions. Designers should reserve interfaces and memory bandwidth for the largest credible implementation rather than assume that any future algorithm will fit automatically.
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Aerospace, industrial, communications and critical-infrastructure equipment can remain operational for many years, outliving the assumptions made when its silicon was designed. Lifecycle-controlled eFPGA updates let operators align cryptography with new mandates, certificate policies and threat models while retaining the original SoC. Long-life deployments still need a maintenance authority, a tested update channel and a plan for when the reserved region reaches its capacity.
7. Reduce redesign exposure and lifecycle cost
Post-silicon adaptability can remove some redesign cycles and reduce total cost of ownership when an algorithm or protocol changes. The economic benefit is workload-specific: it depends on mask and validation costs, field-service logistics, schedule risk, device volume and the size of the programmable region. No independent dollar estimate or time-to-market benchmark has been published for Menta eFPGA, so a business case should model those variables rather than assume a universal saving.
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8. Coordinate hardware and software updates
Crypto agility works best when firmware, drivers, protocol stacks and hardware accelerators are versioned together. EPI says Menta supplies Origami Programmer, which generates a bitstream optimized for Menta’s architecture. That flow can support a coordinated algorithm update instead of forcing software to emulate a new primitive that the original fixed hardware cannot execute efficiently. The integration team still has to define APIs, interrupt behavior, memory ownership, rollback rules and compatibility tests.
9. Use an implementation ecosystem
An eFPGA project spans RTL or IP integration, physical design, cryptographic implementation, post-quantum algorithms, bitstream tooling and silicon bring-up. Menta identifies Presto Engineering for ASIC industrialization and lists KiviCore, PQShield and PQSecure for cryptographic or post-quantum components. Their current scopes, licensing terms, geographic coverage and commercial availability should be verified directly before a program selects a partner.
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Fixed crypto IP, external FPGA or embedded eFPGA?
| Decision axis | Fixed-function crypto IP | External FPGA accelerator | Menta embedded eFPGA |
|---|---|---|---|
| Post-deployment updates | Algorithm changes generally require a new silicon revision. | Reconfigurable, subject to board access and FPGA update controls. | Reconfigurable inside the SoC, subject to reserved capacity and secure bitstream controls. |
| Chip-to-chip exposure | None for the integrated block. | Present on the link between the SoC and FPGA; it must be authenticated and protected. | No external crypto link; the programmable logic is on-chip. |
| Latency and power | Usually predictable after implementation. | Includes link, package and board overhead. | Can avoid an external link, but results depend on placement, routing, clocks and workload. |
| Area and timing closure | Optimized for the chosen algorithm. | Consumes a separate package, board area and power budget. | Consumes reserved SoC area and routing resources; timing must be closed with the rest of the design. |
| Certification and secure updates | One primary hardware configuration, but later changes require requalification. | Requires FPGA bitstream authentication, key management and board-level validation. | Requires authenticated, versioned eFPGA bitstreams plus SoC boot, recovery and certification processes. |
| Supply-chain and foundry portability | Depends on the selected IP and process. | Depends on the external FPGA vendor and availability. | Depends on Menta’s integration support and the target ASIC process; portability must be confirmed per foundry and node. |
| Lifecycle cost | Lower flexibility, potentially higher redesign exposure. | Recurring component, board and field-maintenance costs. | Higher initial integration complexity in exchange for post-silicon adaptability; no public, context-complete cost figure is stated. |
| Post-quantum adoption | Only if the selected block already supports the required algorithm. | Can load new implementations if capacity and interfaces suffice. | Can host new implementations or accelerators if the reserved eFPGA resources and memory interfaces are adequate. |
How to design a crypto-agile eFPGA implementation
- Define the change envelope. List likely replacements, post-quantum candidates, key sizes, protocol modes, throughput targets and memory requirements over the product’s planned life.
- Reserve the right interfaces. Provide controlled access to keys, secure memory, DMA, interrupts, clocks and data paths without exposing secrets to unauthorised logic.
- Specify the update trust chain. Decide who signs bitstreams, how devices authenticate them, how anti-rollback works, how keys are rotated and how a failed update recovers.
- Plan certification evidence. Treat every reconfigurable implementation as a versioned security target with test vectors, side-channel analysis, fault testing and applicable certification impact assessments.
- Co-design firmware and hardware. Define stable APIs and capability reporting so software can select an algorithm version without silently falling back to an unsafe path.
- Close physical design with realistic worst cases. Compile representative cryptographic and post-quantum configurations, then check area, timing, power, thermal limits and secure-isolation constraints before tape-out.
- Test field operation. Exercise staged rollout, interruption, rollback, recovery, key revocation and fleet inventory in the same environments where devices will operate.
What the public evidence establishes
Menta reported AIST adoption of its eFPGA IP for cryptography and hardware-security programs on April 22, 2026. In that announcement, CEO Vincent Markus said, “Security is no longer a feature — it is becoming the organizing principle of modern semiconductor design.” He also said systems must adapt to threats that do not yet exist and described Menta’s technology as programmable, trusted and performant throughout the lifecycle.
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The public sources identify the capability and integration direction, but they do not provide a context-complete Menta benchmark for area, power, throughput, latency, redesign dollars or time to market. Those figures must come from a program-specific synthesis, implementation and security review.
The Bottom Line
Menta eFPGA is most compelling when an ASIC or SoC must survive changing algorithms, post-quantum migration and a long field life. It provides the hardware update point; secure provisioning, authenticated updates, certification and careful capacity planning determine whether that flexibility becomes dependable crypto agility.
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