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Yes—European RISC-V adoption is gaining momentum, especially in automotive computing and high-performance computing. The evidence so far points to coordinated ecosystem-building: funded engineering programmes, processor and software development, prototypes and future product plans. It does not yet establish widespread deployment or mass-market production.

Why RISC-V is gaining ground in Europe

RISC-V is an open instruction-set architecture (ISA): the specification for the instructions a processor understands. Its openness can lower licensing barriers and give designers more flexibility than a proprietary ISA. That is an opportunity, not a shortcut to a finished chip. A production-ready system still needs dependable silicon, software support, security, and—particularly in cars—safety validation and certification.

European efforts connect those practical needs with a broader goal: developing more of the processor value chain in Europe. The European Commission’s 2026 policy text says Europe is investing around €500 million in open RISC-V through the Chips Joint Undertaking. That is a policy-level investment figure, not a budget for one processor or evidence that products are already shipping at scale.

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What the main European initiatives are building

Initiative Focus and maturity Funding and timing reported
European Commission Vehicle of the Future collaboration Pre-competitive collaboration on a RISC-V automotive hardware platform. Its roadmap covers scalable real-time control, high-performance application processors, AI/ML accelerators and system integration. This is a roadmap, not a production vehicle platform. Funding: not stated (European Commission Vehicle of the Future, 5 November 2024). Deployment date: not stated.
Rigoletto Funded engineering programme coordinated by Infineon, with NXP and STMicroelectronics among its participants. It turns automotive RISC-V ambitions into a multi-year development project. Total cost €65,160,523.27; EU contribution €18,738,887.95. Project dates: 1 July 2025–30 June 2028 (European Commission CORDIS, 2025; grant agreement signed 19 May 2025).
Infineon AURIX RISC-V MCU family Infineon announced a future RISC-V family under its AURIX automotive microcontroller brand. Partners are already using a virtual prototype and software development kit; these are development tools, not proof of shipping silicon. Launch described as “in coming years”; exact date and product pricing: not stated (Infineon, 6 March 2025).
DARE European high-performance computing programme. Codasip was selected for the high-end processor work; the programme aims to build a European supercomputing compute stack with RISC-V processors and accelerators. First three-year programme phase funded at €240 million by the European Union (Codasip, 6 March 2025). A product deployment date: not stated.
ISOLDE Reports progress toward high-performance, safe and secure RISC-V ecosystems for automotive, IoT, smart-home and space applications. This is ecosystem development, not evidence that all those sectors have adopted production RISC-V chips. Funding and deployment date: not stated (2025 reporting period).

Automotive is the clearest near-term adoption path

The Commission’s automotive roadmap spans both real-time control and higher-performance computing. Those are different jobs: control processors handle predictable, time-critical functions, while application processors and accelerators support more demanding workloads. System integration matters because a vehicle needs these components, their software and their safety properties to work together.

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Rigoletto adds a concrete funded programme to that policy direction, while Infineon’s AURIX announcement takes a further step toward a named future product family. The virtual prototype and software development kit let partners work on software and integration before launch; they should not be mistaken for a production-ready MCU. Infineon said the new family would become part of its established AURIX automotive microcontroller brand.

DARE makes high-performance computing a second major lane

DARE is aimed at a European supercomputing stack rather than a car-specific processor. Codasip described the planned stack as combining high-performance and energy-efficient RISC-V processors and accelerators designed and developed in Europe. Its announced €240 million applies to the first three-year phase of the programme; it is not a stated chip price or a guarantee that the resulting systems are already available.

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2Pcs Type-C USB CH32V003 Development Board Minimum System core Board for Nano RISC-V
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  • Power by TYPE-C USB

This work connects RISC-V to technological sovereignty: the effort to strengthen European control over important technology and supply-chain capabilities. European Commission CORDIS reporting also describes work on RISC-V processor IP, tools and software stacks intended to localize more of the value chain. Local design and software development can strengthen that chain, but do not by themselves establish where chips will be manufactured or eliminate reliance on non-European suppliers.

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How close is Europe to production?

The initiatives are at different stages, so “adoption” should not be read as one uniform level of readiness. A useful distinction is between:

Rank #3
AITRIP ESP32-C3 Mini Development Board, 4MB Flash Core Board ESP32 Super Mini Development Board ESP32 Development Board WiFi Bluetooth (2PCS)
  • The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
  • It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
  • It supports four serial interfaces, including UART, I2C, and SPI.
  • The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
  • Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
  • Roadmap: defines what a future platform should cover, without demonstrating that the platform is built.
  • Funded project: allocates resources and work to engineering objectives, but does not guarantee a production outcome.
  • Prototype and development tools: support early software and integration work, but are not finished, qualified products.
  • Shipping silicon: a product is available, though availability alone does not prove broad deployment or adoption.

The evidence here establishes European policy work, funded development, a virtual automotive prototype and announced future products. It does not establish broad European production volumes or industry-wide deployment. For automotive use, the remaining tests include safety and security, software compatibility, manufacturing arrangements and certification. The RISC-V Summit Europe programme likewise frames the next challenge as moving from early adoption toward industry-wide deployment, with safety, security and software ecosystem work still central.

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  • Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
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waveshare ESP32-C6 RISC-V Microcontroller Development Board Integrated WiFi 6, Bluetooth 5 and IEEE 802.15.4 (Zigbee 3.0&Thread), Adopts ESP32-C6-WROOM-1-N8 Module, Support USB and UART Development
  • ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
  • Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
  • Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
  • Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
  • Comes with online examples and tutorials for ESP-IDF development environment

What to watch next

  • Whether Rigoletto’s work produces demonstrable platform components and integration results during its stated project period.
  • Whether Infineon’s virtual-prototype work progresses to silicon, and whether the announced AURIX family reaches launch as planned.
  • Whether DARE’s processor and accelerator work translates into usable European high-performance computing systems.
  • Whether software, debug, safety and security support mature alongside the hardware, and whether products reach deployment beyond pilot or development settings.

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