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Microchip announced PolarFire FPGA and PolarFire SoC solution stacks for smart robotics and medical imaging on December 12, 2024. They package hardware with application-focused firmware, IP cores, interfaces, reference designs, evaluation kits and development tools to help teams build power- and thermally constrained intelligent-edge systems. They are development platforms—not finished robots or medical-imaging products.
What Microchip’s solution stacks include
A solution stack is a set of hardware and software resources organized around an application. Microchip’s announcement describes stacks intended to reduce development effort for systems that process data close to sensors and other edge devices.
- Firmware and IP cores for AI-assisted 4K60 computer vision.
- Ready-to-use sensor and camera interfaces.
- Integrated hardware for high-speed Ethernet protocols.
- Development tools, reference designs and evaluation kits that complement the stacks.
The underlying device can vary by application: Microchip’s solution-stack overview identifies PolarFire FPGA, PolarFire SoC, SmartFusion 2 and IGLOO 2 FPGA as possible platforms. The announcement names C/C++, RTL, SmartHLS IDE, VectorBlox Accelerator SDK and Libero SoC Design Suite among the software flows.
What the robotics stack is designed to help build
For robotics, the focus is deterministic, low-power processing near sensors and actuators. Microchip lists AI-assisted computer vision, real-time processing with ROS 2-compatible cores, coordinate transformation and industrial networking support. These capabilities can form part of a robot’s perception and control pipeline; they do not provide a complete autonomous robot, application, or deployment-ready safety system.
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Robotics capabilities at a glance
- Vision: Firmware and IP for AI-assisted 4K60 computer vision, plus camera interfaces.
- Real-time processing: ROS 2-compatible cores for perception and coordinate transformation.
- Industrial connectivity: Support for time-sensitive networking protocols and OPC UA.
- Edge implementation: FPGA-based processing intended for power- and thermally constrained systems.
What the medical-imaging stack is designed to help build
Microchip’s medical-imaging materials position its FPGAs for compact, low-power systems that handle high-resolution data and real-time computing. They also describe AI-powered analysis and security as relevant capabilities. These are platform attributes for product developers, not a claim that a PolarFire design is itself a cleared or approved medical device.
Sensor data and AI workflows
One specifically identified component is the PolarFire FPGA Ethernet Sensor Bridge for NVIDIA Holoscan. Microchip describes it as a way to move high-speed sensor data into AI-processing workflows used in medical and robotic applications. A product team still needs to determine whether the bridge, interfaces and data path fit its sensors, throughput, latency and system requirements.
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- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
How PolarFire SoC differs from an FPGA-only approach
PolarFire SoC combines programmable FPGA resources with embedded processor resources. Microchip describes the family as suited to edge AI, imaging and video pipelines and identifies the Mi-V RISC-V ecosystem. This makes it relevant to teams that want processor-based control or software alongside FPGA acceleration, rather than treating the design as programmable logic alone. The exact processor and fabric configuration depends on the device selected; the announcement does not specify a single configuration for every stack.
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| Area | Robotics | Medical imaging |
|---|---|---|
| Highlighted need | Deterministic, low-power processing near sensors and actuators | Compact, low-power processing for high-resolution data and real-time computing |
| Named capabilities | AI-assisted vision, ROS 2-compatible real-time perception and coordinate transformation | AI-powered analysis, security, and high-speed sensor-data handling |
| Connectivity or workflow example | Time-sensitive networking and OPC UA | PolarFire FPGA Ethernet Sensor Bridge for NVIDIA Holoscan |
| What the stack is | A development platform and set of resources, not a finished application or end product | |
| Performance figures, exact kit models and project cost | Not stated in Microchip’s December 12, 2024 announcement | |
Tools, functional safety and development resources
Microchip names C/C++, RTL, SmartHLS IDE, VectorBlox Accelerator SDK and Libero SoC Design Suite as development flows associated with the stacks. Its announcement states that Libero has been certified for applications needing IEC 61503 SIL 3 functional safety. That statement concerns the design tool’s certification for applications with that requirement; it does not certify a customer’s complete device or replace system-level safety engineering and assessment.
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- [FPGA Chip] GW2AR-18 QN88 FPGA Chip containing 20736 LUT4 logic cells and 15552 Filp-Flops.There are 2 PLL in this FPGA chip, and many DSP units supporting 18 bit x 18 bit multiplication
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Microchip’s solution-stack overview also describes evaluation kits, development tools, IP cores and reference designs as supporting resources. Teams considering a PolarFire SoC FPGA development board or another kit should confirm the exact model, device, included interfaces, software access and current availability with Microchip or an authorized seller; the announcement does not identify a universal kit SKU or price.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to assess whether a stack fits your project
Use the application description as a starting point, then verify the design constraints that the public announcement does not quantify. In particular, compare prospective platforms on:
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- Power and thermal budget for the target enclosure and operating environment.
- FPGA fabric and processor resources needed by the application.
- Camera and sensor-interface compatibility.
- Real-time robotics and industrial-networking requirements.
- AI/ML development flow and the tools the engineering team can support.
- Functional-safety and security requirements, including what evidence and certification the finished product needs.
- Availability of the development kit, along with total hardware and tool costs.
Microchip vice president of marketing and strategy for the FPGA business unit Shakeel Peera framed the target as secure, functionally safe, AI-assisted industrial automation and portable medical imaging in small, thermally stressed footprints. That describes the intended problem space; teams should validate their own workload, interfaces and compliance needs against the particular device and development resources they plan to use.
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