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A reported teardown of Huawei’s Kirin 9050 Pro describes a vertically bonded chip design with compute and cache-related functions distributed across two dies. The reported die measurements are close to those attributed to the Kirin 9030S, but they are measurements of an individual layer—not proof that the complete package is smaller. Huawei confirms that the phone chip uses its LogicFolding architecture; the reported SMIC N+3 and N+2 process assignments have not been confirmed by Huawei or SMIC.
What the Kirin 9050 Pro teardown reportedly found
Wccftech reported on October 2, 2026, that Kurnal Insights published die-shot images identified as HiSilicon Hi36E0, or Kirin 9050. Its account describes compute and SRAM/cache functions on vertically bonded dies. A separate teardown account from Notebookcheck, published October 3, describes copper-to-copper hybrid bonding and through-silicon vias (TSVs) carrying power and signals between layers.
Notebookcheck attributes its architectural description to Geekerwan’s teardown. In that interpretation, a secondary layer contains cache, I/O interfaces and phase-locked loops (PLLs), while major functional blocks extend across both dies. The account reports about 80,000 TSVs and says TSV keep-out zones consume around 8% of the bottom die’s usable area. Those details are teardown interpretations, not a complete official chip specification.
How large are the reported dies?
Wccftech gives the dimensions of each die as 11.13 mm × 10.84 mm, or 120.65 mm². It compares that reported layer area with a 122 mm² figure for the Kirin 9030S. Both figures are reported measurements, not independently verified metrology.
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The distinction between a die and a package matters: 120.65 mm² is presented as the area of a die layer. The reports do not establish that as the total footprint of the stacked package. Nor does vertical bonding make either individual die smaller; it places layers on top of one another, which can concentrate more functions within a given package footprint.
The reported areas alone also do not establish a manufacturing-yield advantage. Smaller individual dies could affect die yield, while stacking introduces additional assembly and package-yield considerations. The available reports do not provide measured yield data.
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Are the N+3 and N+2 process assignments confirmed?
No. Wccftech attributes the claim that the compute die uses SMIC N+3 and the SRAM/cache die uses N+2 to a tipster. Notebookcheck repeats the split but explicitly notes that neither Huawei nor SMIC has directly confirmed those node assignments. They should be treated as reported claims, not verified specifications.
Huawei’s September 9, 2026 announcement about the Kirin 9050 Pro does not assign a process node to either layer. It describes the chip’s LogicFolding architecture instead. The company’s description establishes its stated architecture, not the foundry process used for each die.
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What Huawei means by LogicFolding
Huawei describes LogicFolding as a way to distribute selected chip areas across vertically connected levels using hybrid bonding. The company says this replaces some long horizontal connections with shorter vertical paths, with the aim of improving integration density and potentially performance or energy use. The description is Huawei’s account of its commercial architecture; it does not independently verify the teardown’s layer-by-layer assignments.
Huawei says LogicFolding raises density to 238 million transistors per square millimeter from around 155 million/mm², a stated 55% increase. It also says typical compute-block wire lengths fall by around 20%, and critical paths by up to 70%. These are company-reported comparisons, not independent measurements.
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What Huawei claims about Kirin 9050 Pro performance
Huawei’s launch announcement reports a 70 TOPS neural processing unit (NPU), which it says is 141% above its predecessor. It also claims a 42% GPU performance increase and an 18% CPU benchmark increase. The announcement does not make these independent test results, so they should be read as vendor claims.
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How to interpret the “smaller footprint” claim
The reported 120.65 mm² figure is slightly below the 122 mm² Kirin 9030S comparison cited by Wccftech. That is a narrow, reported die-area comparison—not evidence that the Kirin 9050 Pro package is smaller than its predecessor or than chips generally. The sources do not provide a complete apples-to-apples comparison of package dimensions, performance, power, yield or manufacturing availability.
Notebookcheck compares the approach with AMD’s 3D V-Cache only in the limited sense that separately manufactured silicon is bonded together. Its account says LogicFolding distributes major blocks across both dies, so the analogy should not be taken to mean the two architectures are the same.
Which phone uses the Kirin 9050 Pro?
Huawei says the Kirin 9050 Pro debuts in the Mate XT 2. That makes the phone the chip’s launch platform; the announcement alone does not establish the phone’s price, availability by region or current stock.
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Quick Recap
Sources
- Wccftech, October 2, 2026: die-shot report and attributed measurements
- Notebookcheck, October 3, 2026: account of Geekerwan’s teardown and node-confirmation caveat
- Huawei Germany, September 9, 2026: LogicFolding announcement and vendor claims
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