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Flip-chip cracks and delamination are driven in part by thermal-expansion mismatch among the die, bumps, underfill, and substrate. Underfill supports and protects the interconnects, but it also becomes part of the package’s mechanical system. A 2011 AMD finite-element analysis (FEA) reported that lower underfill CTE and a taller fillet could help limit crack growth in the modeled case; it did not establish universal material specifications.
How do cracks and delamination form in flip-chip packages?
In a flip-chip assembly, the die is mounted face down and connects to a package substrate or circuit board through bumps. Underfill occupies the gap between the die and substrate. Because the package layers expand and contract differently as temperature changes, thermal cycling can create stresses at their interfaces. Defects such as voids or microcracks can contribute to delamination.
As Zhen Zhang, identified in the 2011 EE Times article as a Senior Packaging Engineer at AMD, put it: “In flip-chip packages, the mismatch in coefficients of thermal expansion (CTE) of the various layers induces stresses that can result in delamination.” The relevant mismatch is not just a single material comparison; the die, interconnects, underfill, and substrate interact as an assembly.
What does underfill do—and why can it affect reliability?
Underfill couples the die and substrate, supports the bumps, and helps protect them from moisture and other environmental hazards. It can redistribute thermomechanical stress away from the interconnect region, but its properties and the quality of the finished interface matter too.
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- Material behavior: CTE, modulus, and glass-transition temperature (Tg) influence the mechanical response across the package’s temperature range.
- Process behavior: Uncured flow and cured behavior both matter; voids, cure conditions, and interface preparation can affect the finished assembly.
- Geometry: Underfill fillet shape and height can influence stresses near the die edge, where the modeled crack was located.
Consequently, choosing an underfill is not simply a matter of seeking the stiffest material or minimizing one property in isolation. The material, geometry, interfaces, manufacturing process, and intended thermal and mechanical conditions work together.
What did the 2011 AMD FEA report?
David Cadge’s April 20, 2011, EE Times article describes an AMD engineering study using Dassault Systèmes SIMULIA Abaqus. The team modeled a pre-existing crack at the corner of the chip/underfill interface and examined underfill modulus and CTE, fillet height, crack-front shape, and crack size. The article reports a 26,000-element global model, as well as a global-local approach with approximately 19,400 elements in its global model and 18,200 in its local model.
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| Reported finding | How to interpret it |
|---|---|
| Select underfill with low CTE | A recommendation reported for the modeled case, not a universal specification. |
| Increase fillet height if possible | A geometry recommendation from that analysis; feasibility and effect depend on package design and process. |
| Keep Tg as low as possible while remaining above the upper bound of the test or service temperature range | The article’s reported guidance for its analysis; the relevant temperature range must be defined for the actual application. |
| Modulus effect was minimal | This was the reported result in the particular analysis, not proof that modulus is unimportant in other package or material systems. |
The article also gives specific conditions for plotted comparisons: one comparison of energy release rate against underfill modulus used a fixed 10 μm crack, and several comparisons state a thermal excursion of ΔT = 1°C. That excursion is a model condition, not the package’s full service range. Crack size and front shape were among the study variables, so its conclusions should be read in the context of the modeled flaw and geometry.
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Zhang characterized the analysis as providing “reliability data for all flip-chips in which underfill is incorporated—from package to board level, and from assembly to service conditions.” That is his description of the study’s utility, not evidence that one model validates every flip-chip design.
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How should engineers use the findings when comparing underfills?
Use the AMD results to identify questions for a package-specific study, not to rank materials or copy a recipe. Compare candidate materials in the actual package architecture and against its intended service and test profile. A useful review includes:
- Underfill CTE and its relationship to the other package materials, including the vertical-direction relationship with solder-bump CTE.
- Modulus and Tg over the relevant temperature range.
- Uncured flow, cure behavior, adhesion, and interface preparation.
- Void risk and achievable fillet geometry.
- Reliability under the tests that represent the intended application.
A separate coreless-package study reported material-dependent outcomes in temperature-cycle, thermal-shock, and highly accelerated stress testing; one tested amide-based material was associated with die cracks. That result is specific to the tested coreless package and material, and should not be generalized to all flip-chip designs.
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Why FEA needs package-specific validation
FEA can organize a parameter study by making it possible to vary properties and crack geometry systematically. Its conclusions still depend on the modeled materials, interfaces, geometry, flaw assumptions, and loading conditions. For a defensible design decision, use a model suited to the package in question and corroborate it with physical reliability testing under relevant conditions. The supporting review literature likewise emphasizes process and material behavior alongside stress redistribution.
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The 2011 article also repeats a claim that more than one billion devices per year were manufactured using flip-chips, but does not identify the figure’s original publisher or year. It should not be treated as a current industry statistic.
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