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izmo Limited announced on 7 October 2026 that its semiconductor subsidiary, izmo Microsystems Pvt. Ltd., has signed a memorandum of understanding with IIT Madras for Phase II of the MeitY-sponsored Centre for Programmable Photonic Integrated Circuits and Systems (CPPICS). The five-year program is called SPECTRA (Silicon Photonics Enabled Cutting-edge Technology Research and Applications). The stated outlay is ₹99.94 crore. Everything about Phase II below comes from izmo’s own announcement, so the targets are plans, not delivered products.
The deal and the money
According to izmo’s announcement, the total project outlay is ₹99.94 crore over five years. The split it gives is:
- ₹97.54 crore from MeitY (Ministry of Electronics and Information Technology).
- ₹2.40 crore from izmo Microsystems, as a cash and in-kind commitment.
The announcement was issued by izmo Limited through PR Newswire. We found no independent confirmation of disbursement, a detailed milestone schedule, or completion status.
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What CPPICS had already launched
Phase II builds on work that MeitY reported earlier. On 24 April 2026, the CPPICS centre at IIT Madras launched an indigenous silicon photonics process design kit (PDK) and a universal packaged programmable photonic integrated circuit (PPIC) test engine. MeitY said the PDK had more than 50 verified components. It described the PDK as design infrastructure for industry, startups, academic institutions and defence R&D organizations. It also called CPPICS a shared national facility.
MeitY named SilTerra Malaysia as the silicon photonics foundry partner and izmo Microsystems as the photonic IC packaging partner. It quoted CPPICS Chief Investigator Prof. Bijoy Krishna Das: “Starting in Q3 of this financial year, our center will enable Silicon Photonics MPW fabrication runs while offering comprehensive testing, packaging, and module characterization.” That is a statement about planned capability, not proof that multi-project wafer runs have started.
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- Circuit details can be examined under a microscope.
Amitesh Sinha, Additional Secretary at MeitY and CEO of the India Semiconductor Mission, said: “With appropriate industry partner, this kind of technology can be supported under upcoming ISM 2.0 (R&D vertical) for further technology improvements and products development.” This describes possible future support under conditions. It does not confirm a committed Phase II funding stream.
What Phase II aims to build
izmo describes Phase II as a shift from research toward commercially deployable products. The scope covers photonic integrated circuit (PIC) design, fabrication, characterization, advanced packaging, testing and system integration.
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- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
Stated targets
- A 1.6 Tbps silicon photonics transceiver engine at 1550 nm, for high-performance computing and data-center routing.
- Microwave photonic engines operating beyond 50 GHz, for advanced wireless communications.
- Integrated quantum random number generation and quantum key distribution (QRNG/QKD) systems.
- Photonic processors for AI workloads.
- A silicon photonics PDK with more than 100 IP blocks for 200 mm wafer platforms.
The last item should not be confused with the PDK launched in April. That one is reported by MeitY as having more than 50 verified components. The 100-plus figure is a later target from izmo’s release.
How the target areas differ
| Area | Stated Phase II target | Main integration challenge |
|---|---|---|
| Data-center optics | 1.6 Tbps transceiver engine, 1550 nm | Co-packaged optics interface, fiber attachment, thermal management |
| Advanced wireless | Microwave photonic engines beyond 50 GHz | High-speed testing and system integration |
| Quantum photonics | Integrated QRNG/QKD systems | Not stated in the announcement |
| AI computing | Photonic processors for AI workloads | PIC and electronic IC co-integration |
The challenge column pairs areas with the packaging and integration tasks the release lists. The release does not map each task to a specific product, so read the pairings as indicative.
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- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
izmo Microsystems’ role
izmo’s contribution centers on packaging and industrialization. Its announcement lists packaging architecture and co-packaged optics (CPO) interface definition, PIC-EIC (electronic IC) co-integration, fiber alignment and attachment, production-grade packaging, process optimization, prototype assembly and reliability validation. The longer-term aim is a certified CPO design rule and service capability.
Dinanath Soni, Director of izmo Microsystems, framed it this way: “The challenge is no longer only designing the photonic chip. Converting that chip into a reliable product requires precision packaging, fiber attachment, electronic-photonic integration, thermal management and high-speed testing.”
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- AUTHENTIC SILICON SAMPLE: Real silicon wafer die sample featuring genuine wafer surface patterns, designed for semiconductor learning, research demonstration, and technology display purposes.
- NON-FUNCTIONAL SPECIMEN: This silicon sample is a display and educational specimen only. It is not an electronic component and does not perform computing or electrical functions.
- SEMICONDUCTOR EDUCATION USE: Suitable for classrooms, laboratories, engineering courses, STEM activities, and demonstrations of wafer structures and semiconductor manufacturing concepts.
- TECHNOLOGY DISPLAY ITEM: Ideal for exhibitions, science displays, collections, and demonstrations related to microelectronics and semiconductor technology.
- INDIVIDUAL PACKAGING: Each sample is separately packaged to help maintain surface cleanliness and reduce scratches during storage and handling.
The market figures in the announcement
izmo’s release attributes several estimates to LightCounting. We did not check them against an original LightCounting publication:
- Optical transceiver and related-product sales of $26.8 billion in 2025, up 74% year on year.
- About $40 billion for the optical transceiver market in 2026, with silicon-photonics-based transceivers expected to exceed half of it for the first time.
- Optical chips for transceivers, active optical cables, and near- and co-packaged optics rising from about $4 billion in 2025 to $15 billion by 2031.
What is and isn’t established
This is government-backed R&D and industrial capability building, not a retail product launch. The 1.6 Tbps engine, the beyond-50-GHz microwave engines, the QRNG/QKD systems, the AI processors and the expanded PDK are all stated goals. We found no independent evidence that any of them is deployed or commercially available. The April facility outputs (the PDK and the packaged PPIC test engine) are the parts MeitY has reported as launched.
Quick Recap
Best Value
- AUTHENTIC SILICON SAMPLE: Real silicon wafer die sample featuring genuine wafer surface patterns, designed for semiconductor learning, research demonstration, and technology display purposes.
- NON-FUNCTIONAL SPECIMEN: This silicon sample is a display and educational specimen only. It is not an electronic component and does not perform computing or electrical functions.
- SEMICONDUCTOR EDUCATION USE: Suitable for classrooms, laboratories, engineering courses, STEM activities, and demonstrations of wafer structures and semiconductor manufacturing concepts.
- TECHNOLOGY DISPLAY ITEM: Ideal for exhibitions, science displays, collections, and demonstrations related to microelectronics and semiconductor technology.
- INDIVIDUAL PACKAGING: Each sample is separately packaged to help maintain surface cleanliness and reduce scratches during storage and handling.
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