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In March 2017, Intel said it planned to begin making chips on its 10nm process that year and introduced 22FFL, a separate 22nm low-power FinFET foundry process for mobile and Internet of Things designs. Intel promoted 10nm’s density as unusually high, but the comparison depended on a metric that drew criticism; 22FFL, meanwhile, was pitched as a lower-power alternative to fully depleted silicon-on-insulator processes. These were announcement-era claims, not evidence of either node’s present-day availability or production results.
What Intel announced in March 2017
EE Times reported on March 28, 2017, that Intel planned to start making 10nm chips in 2017. Alongside that roadmap statement, Intel announced 22FFL, a 22nm low-power FinFET process intended for foundry customers designing products such as mobile and IoT devices. The two announcements addressed different aims: Intel presented 10nm around transistor density, while 22FFL emphasized low power, simpler design rules, and cost.
How dense was Intel’s 10nm process?
Intel claimed a density of 100.8 million transistors per square millimeter for 10nm. For comparison, the same 2017 report listed Intel’s 14nm process at 37.5 million transistors per square millimeter. Intel also estimated that contemporary 10nm foundry processes from TSMC and Samsung reached about half its claimed density. These figures were reported as Intel’s 2017 estimates, not independent measurements of competing processes.
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Intel reported these 10nm specifications: 34nm fin pitch, 53nm fin height, 36nm minimum metal pitch, 272nm cell height, and 54nm gate pitch. It also highlighted self-aligned quad patterning, fins it described as 25% taller and more closely packed than those on its 14nm node, contact-over-active-gate technology, and a single dummy gate rather than a double dummy gate.
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Was Intel’s density metric an apples-to-apples comparison?
The number was not a count of every transistor in a representative finished chip. Intel’s proposed metric averaged the area of two cell types: a small two-input NAND cell and a larger scan flip-flop cell. Intel senior fellow and process-architecture director Mark Bohr called it “a comprehensive, quantitative and honest metric.” The chosen cells and their weighting therefore matter when interpreting the result: a different mix of cells or design rules can change the estimated density.
Industry responses reflected that disagreement. Analyst G. Dan Hutcheson welcomed moving beyond marketing-driven node names and argued that density was central to Moore’s law. Analyst David Kanter described Intel’s density as impressive but said it would matter only once the process was in production. A TSMC spokeswoman questioned how Intel arrived at its calculation and pointed to layout and design rules as additional factors in die size and competitiveness. The announcement established Intel’s own measurement and estimate, not a settled, directly comparable ranking of foundry technologies.
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What 22FFL was designed to do
Intel positioned 22FFL as a low-power FinFET option for mobile and IoT designs, and as an alternative to competitors’ fully depleted silicon-on-insulator (FD-SOI) processes. Intel said the process combined high-performance and low-power transistors, with leakage 100 times lower than peers in 28nm. It also described simplified design rules and interconnects intended to bring costs closer to 28nm. Those leakage and cost statements were Intel’s claims in 2017, not independently established comparisons.
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A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11The announcement-era 22FFL specifications were 45nm fin pitch, 108nm gate pitch, 90nm metal pitch, 630nm logic-cell height, 18.8 million transistors per square millimeter, and a 0.088µm² SRAM bit cell. The density figure is far below Intel’s claimed 10nm figure, but the nodes were not presented for identical purposes: 22FFL prioritized low-power applications and design economics rather than maximum density.
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How ready was 22FFL at announcement?
Intel planned to ramp 22FFL before the end of 2017. EE Times reported that a process-design kit (PDK) version 0.5 was available at the time of the announcement and that version 1.0 was expected by June. These were schedule statements, not confirmation that the ramp or PDK release occurred as planned.
For context, GlobalFoundries senior vice president Alain Mutricy said the company’s competing 22nm process was fully qualified for production at Fab 1 in Dresden and that GlobalFoundries planned to increase Dresden 22nm capacity by 40% by 2020. Those were company statements reported by EE Times; they do not independently verify production output or the later capacity outcome.
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- 20 cores (8 P-cores plus 12 E-cores) and 28 threads. Discrete graphics required
- Up to 5.6 GHz with Turbo Boost Max Technology 3.0 gives you smooth game play, high frame rates, and rapid responsiveness
- Compatible with Intel 600-series (with potential BIOS update) or 700-series chipset-based motherboards
- DDR4 and DDR5 platform support cuts your load times and gives you the space to run the most demanding games
How to compare the two announcements
| Comparison point | Intel 10nm, as reported in 2017 | Intel 22FFL, as reported in 2017 |
|---|---|---|
| Primary positioning | High transistor density | Low-power FinFET foundry process for mobile and IoT; alternative to FD-SOI |
| Claimed density | 100.8 million transistors/mm², Intel’s 2017 figure using an average of a small two-input NAND and a larger scan flip-flop | 18.8 million transistors/mm², Intel’s 2017 figure; its density methodology is not specified in the supplied report |
| Pitch and cell figures | 34nm fin pitch; 53nm fin height; 36nm minimum metal pitch; 54nm gate pitch; 272nm cell height | 45nm fin pitch; 90nm metal pitch; 108nm gate pitch; 630nm logic-cell height; 0.088µm² SRAM bit cell |
| Power and leakage emphasis | Not stated as the central announcement focus in the report | Intel claimed leakage 100 times lower than peers in 28nm |
| Design and cost emphasis | Self-aligned quad patterning and other FinFET structure changes highlighted | Simplified design rules and interconnects intended to approach 28nm cost |
| Readiness statement | Intel planned to begin making chips in 2017 | Intel planned to ramp before the end of 2017; PDK v0.5 available and v1.0 expected by June |
The table captures the announcement’s stated specifications and plans. It does not make the density values directly equivalent: the report explains Intel’s 10nm cell-average method, but does not specify a matching method for 22FFL.
What the 2017 report does—and does not—establish
The announcement is useful for understanding Intel’s 2017 process strategy and the arguments over how to compare fabrication nodes. It documents Intel’s targets, specifications, and competitive claims at that time. It does not establish the nodes’ current production status, customer list, yields, or commercial availability in 2026; those outcomes cannot be inferred from a roadmap or a planned ramp alone.
Quick Recap
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- Game without compromise. Play harder and work smarter with Intel Core 14th Gen processors
- 24 cores (8 P-cores plus 16 E-cores) and 32 threads. Integrated Intel UHD Graphics 770 included
- Leading max clock speed of up to 6.0 GHz gives you smoother game play, higher frame rates, and rapid responsiveness
- Compatible with Intel 600-series (with potential BIOS update) or 700-series chipset-based motherboards
- DDR4 and DDR5 platform support cuts your load times and gives you the space to run the most demanding games
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