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IIT Delhi researchers have built a working micro-GPU design on a Spartan-7 FPGA, a reconfigurable chip used for prototyping. The chip itself has not been fabricated. Their stated next step is to realise the design as a 65nm ASIC, a custom silicon chip, and as of the October 9, 2026 interview that reported the project, they did not have a domestic facility to make it.
What the team has actually demonstrated
The project was developed by MTech students Nammi Akash and M Ravi Teja, working under IIT Delhi Electrical Engineering professors Jayadeva and Kaushik Saha. What exists today is a programmable graphics processor mapped onto a Spartan-7 FPGA. An FPGA is a chip whose logic can be reconfigured after manufacture, which makes it a practical way to test a hardware design before committing to silicon. The result is a demonstration of the design running on that platform, not a finished product that can be bought or shipped.
FPGA prototype versus planned ASIC
The distinction matters because the two implementations serve different purposes. The table below summarises what the reporting establishes for each.
| Attribute | Current FPGA implementation | Planned ASIC realisation |
|---|---|---|
| Hardware type | Reconfigurable FPGA (Spartan-7 platform) | Fixed-function custom chip (VLSI ASIC) |
| Status | Demonstrated | Proposed; not yet fabricated or validated |
| Process node | Not applicable to the FPGA platform in the report | 65nm, per the researchers’ stated target |
| Performance optimisation | Limited to the FPGA mapping | Expected by the team to allow further optimisation; no measured comparison given |
| Power, die area, cost | Not stated in the report | Not stated in the report |
Prof Jayadeva describes the ASIC step as a way to “optimise the performance even more than the current realisation, which is a mapping onto what’s called a Field Programmable Gate Array (FPGA).” The interview does not quantify that gain, so readers should treat it as the team’s expectation rather than a measured result.
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Why 65nm is the sticking point
A 65-nanometre process describes the scale of the transistors on a chip. It is an older, more mature node than the advanced nodes used for leading-edge processors, which is one reason the team considers it a realistic target for a design of this kind. The obstacle is access, not design. Prof Kaushik Saha said, at the time of the interview: “At this moment, in India, we don’t have the fabrication facility for 65-nanometer ASIC chip technology. So we will have to look for fabs abroad.” He added that the team is exploring partnerships with industry, public sector undertakings (PSUs), and government organisations. The report names no partner and no confirmed programme, so the route to fabrication remains open.
The headline describes the goal as India’s first 65nm graphics chip. That is an aim the team has stated, not an achievement the reporting confirms.
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Who it is for
The team is explicit about the niche. Prof Saha said: “We are not aiming to compete with Nvidia.” The target is small, low-power devices where graphics speed is not the priority. He described it as “edge applications on small form-factor devices, handhelds mostly, which consume very little power so that these can be proliferated in the Indian society and population.”
Prof Jayadeva gave three examples of where the micro-GPU could fit:
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- Displays in electric vehicles and similar vehicles
- Medical diagnostic displays
- E-rickshaw meters
These are applications the researchers propose. The reporting does not describe any of them as deployed or under contract. The common requirement is that the screen does not need to refresh at high speed.
The roadmap: what is planned and what is not
The longer-term plan, as described in the interview, includes a vector-style graphics processor with 8 to 16 cores, an optimised compiler, and graphics software tools. These are plans. No core count has been built or tested, and the reporting gives no performance figures for any version of the design.
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The team also hopes that wider availability of the design could help students and startups build applications and more complex designs. The article does not say where the design would be published or under what licence, so there is no public release to download or reproduce.
Can you use it now?
Not as a product. The reporting describes no commercial sale, no release location and no licence. Readers who want to explore programmable hardware on their own can work with an FPGA development board of the same family, but the article does not identify a specific board, and a board alone will not reproduce the IIT design.
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What remains unknown
- Measured performance, power consumption, die area and cost for the prototype or any ASIC version
- Whether a fabrication partner abroad has been selected
- Whether any of the proposed applications has moved beyond discussion
- Whether, and under what terms, the design will be released to students or startups
Each of these is a question the current reporting leaves open. Readers following the project should look for a fabrication announcement, a named partner, or a published technical paper before assuming any of them has happened. The primary source for the details above is the India Today Tech interview from October 9, 2026.
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