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IBM and Xilinx announced a licensing and technology agreement on July 25, 2000, to put IBM PowerPC processor cores and the CoreConnect bus into Xilinx Virtex-II FPGAs. The commercial result was the Virtex-II Pro family, which combined hard PowerPC 405 processors with programmable FPGA logic so designers could divide a system’s work between software and custom hardware.
What the IBM–Xilinx agreement covered
The companies said they would combine their technologies for chips aimed at communications, storage and consumer applications. IBM licensed its PowerPC processor cores and CoreConnect bus for integration into Xilinx’s Virtex-II FPGA platform; IBM was to fabricate the initial devices using its advanced manufacturing processes. The announcement was reported by EE Times on July 26, 2000.
In practical terms, IBM contributed processor and interconnect IP, while Xilinx combined those elements with its programmable logic. The agreement was not simply a plan to load a processor design into the FPGA as configurable logic: the resulting Virtex-II Pro devices included hard processor cores.
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Which Xilinx FPGAs included PowerPC 405 processors?
The relevant product family was Xilinx Virtex-II Pro. Xilinx described these devices as placing an IBM PowerPC processor inside the programmable-logic fabric, with processor I/O available to the internal logic. That arrangement allowed logic in the FPGA to connect closely to the processor.
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Xilinx’s archival product literature listed up to four IBM PowerPC 405 processors per Virtex-II Pro device. It specified 300+ MHz and 420 Dhrystone MIPS for each processor. These are historical, vendor-published specifications, not a guarantee that every device in the family contained four processors or delivered a measured application-level performance result. See Xilinx’s Xcell Journal, Issue 40.
How the hard processor worked with FPGA logic
A hard processor core is implemented as a dedicated block in the chip rather than constructed from the FPGA’s configurable logic. In Virtex-II Pro, this gave designers an IBM PowerPC 405 processor alongside the fabric they could configure for application-specific hardware. CoreConnect provided the associated on-chip bus architecture.
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Xilinx contrasted the PowerPC hard core with MicroBlaze, its soft processor core. The design choice was therefore not simply “processor or FPGA”: a system could use the PowerPC for software-driven tasks and programmable logic for custom or parallel hardware functions, with soft peripherals preserving flexibility. The hard-core approach suited designs seeking processor performance without giving up the ability to tailor surrounding logic.
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Scan for outdated or missing drivers - takes under a minuteDriver Scan →Repair Windows errors before they cause bigger problemsFix Now →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Xilinx described the integration this way: “We will embed this processor within our programmable logic fabric, so all of the processor I/O pins are available to the internal programmable logic for maximum flexibility.” The quote appears in Xcell Journal, Issue 40.
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What the deal meant for system designers
- Hardware/software partitioning: Developers could run control and other software on the PowerPC 405 while implementing selected functions in custom FPGA logic.
- A hard-core performance option: The processor was a dedicated embedded block, distinct from building a soft processor such as MicroBlaze out of configurable fabric.
- Processor-to-logic integration: Xilinx’s stated design allowed processor I/O to be exposed to internal programmable logic, enabling close integration of software and custom hardware.
- A broader toolchain requirement: Developing the system meant configuring both the processor and the FPGA, rather than treating them as separate products.
Wind River addressed that toolchain need through a multi-year OEM agreement announced January 28, 2002. Its tools were designed for Xilinx’s next-generation Virtex-II Platform FPGA with the PowerPC 405, and aimed to help developers configure and program both the CPU core and FPGA device. Wind River said the tools would help developers “rapidly configure and program both the CPU core and Virtex-II Platform FPGA device.” See Wind River’s January 28, 2002 announcement.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to place the platform in context
Virtex-II Pro represents an early-2000s approach to system-on-chip design: a hard general-purpose processor combined with FPGA fabric that users could customize. When comparing it with a soft-core-only FPGA or a later FPGA SoC, the useful distinctions are whether the CPU is hard or soft, its documented performance, the available programmable fabric and interconnect, the software-tool support, and the product’s manufacturing and lifecycle era. The historical specifications and announcements above establish the original design and its intended development path; they do not establish present-day availability, tool compatibility, or lifecycle support.
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