Free tools Windows power users keep installed
One-click scans. No signup required.
iTechGuides is reader-supported. When you buy through links on our site, we may earn an affiliate commission. As an Amazon Associate I earn from qualifying purchases. Learn more
Transistors keep Moore’s Law moving, but not by shrinking alone. Today’s progress combines new transistor shapes with advanced lithography, better wiring and power delivery, and packaging that connects multiple parts of a system. FinFETs gave way to gate-all-around nanosheets as scaling became harder; forksheets and vertically stacked complementary transistors are among the next approaches being developed.
What Moore’s Law means for chips today
Moore’s Law is an industry roadmap, not a physical law that guarantees every new chip will be twice as fast or half as expensive. Its familiar modern shorthand is a doubling of transistor count over time. That progress has historically come from several sources: smaller device dimensions, larger dies, improved circuit design, and changes in how transistors are arranged and connected.
One scaling target used in an undated imec roadmap article is reducing transistor dimensions to 0.7 times their previous value every two years. That is a roadmap figure, not a promise that every manufacturer or process node achieves the same reduction. Chipmakers also use node names that do not directly state a transistor’s physical gate length. A Nature review published in 2023 notes that MOSFET physical gate length has reached below 20 nm; that measurement should not be inferred from a process-node label.
The practical question is whether a new generation improves the combination of power, performance, area and cost—not whether its name sounds smaller. Density gains can come from changing the transistor itself, but also from changing its wiring, power network, packaging, or integration with other components.
#1 Best Overall
- Used Book in Good Condition
Why FinFETs improved on planar transistors
In a planar MOSFET, the channel lies flat and the gate controls it from above. As devices shrink, the gate has a harder time controlling the channel, contributing to short-channel effects and leakage. A FinFET raises the channel into a narrow fin, allowing the gate to control it from three sides. That stronger electrostatic control helped sustain scaling beyond planar designs.
Imec reports that the first commercial 22 nm FinFETs appeared in 2012, and that 7 nm chips were in production using FinFETs when its roadmap article was written. As dimensions and standard-cell heights shrink further, a single fin can become insufficient to provide the needed drive current, while maintaining strong control over the channel becomes more difficult. That is why designers are moving toward structures that wrap the gate around more of the channel.
What comes after FinFET
The next steps change how channels and complementary transistor types are arranged. Gate-all-around (GAA) nanosheets are the closest architectural successor in this sequence; forksheets and complementary FETs (CFETs) are further ways to reduce the space occupied by logic. These approaches are development and roadmap directions, not a guarantee that every one will enter high-volume production on a particular schedule.
Quick wins for a faster PC:
Scan for outdated or missing drivers - takes under a minuteDriver Scan →Clear out junk files and repair common Windows errorsFree Scan →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Rank #2
| Approach | How it is arranged | Why it may help | Status indicated by cited sources |
|---|---|---|---|
| FinFET | A raised fin channel is controlled by a gate on three sides. | Improves channel control compared with a planar MOSFET. | Commercial 22 nm FinFETs appeared in 2012; imec reports 7 nm chips in production with FinFETs when its roadmap was written. |
| GAA nanosheet | Stacked horizontal sheet channels are surrounded by the gate. | Improves electrostatic control and can provide more drive current per footprint. | Identified by ASML and imec as a route beyond FinFET; the cited roadmap sources do not establish a universal production schedule. |
| Forksheet | A dielectric wall separates nMOS and pMOS gate trenches. | Allows the n- and p-type devices to sit closer together. | Imec simulations project area and performance benefits and a possible standard-cell-height reduction from 5T to 4.3T; these are projections, not universal production results. |
| CFET | The nFET is placed vertically above the pFET. | Uses vertical integration to pursue smaller logic and SRAM cells. | Roadmap concept; imec describes a path toward 3T cells, not a guarantee of commercial deployment. |
GAA nanosheets
A GAA nanosheet turns the FinFET channel into one or more horizontal sheets and surrounds each sheet with the gate. In effect, the gate can control the channel around its full perimeter rather than three sides. The sheets can also be designed to support drive current within a compact footprint, making GAA a way to address both electrostatic control and device density.
Forksheets
A forksheet adds a dielectric wall between the gate trenches for n-type and p-type MOSFETs. The wall is intended to let those devices be placed closer together. Imec’s projected move from a 5-track (5T) to a 4.3-track (4.3T) standard-cell height is a simulation-based possibility, not a measured gain applicable to every chip.
CFETs
A CFET stacks the complementary nFET and pFET vertically, or “folds” one above the other. That can save the lateral space normally needed to place the pair side by side. Imec describes this as a route toward 3T logic and SRAM cells. ASML’s 2022 roadmap lists GAA, nanosheets, forksheets and CFETs among possible routes toward the 1 nm generation, but a roadmap destination is not evidence that each structure is already a high-volume product.
Rank #3
Why EUV lithography matters
New transistor shapes do not by themselves create a manufacturable chip: manufacturers also have to pattern the small features and pitches that those designs require. Extreme ultraviolet (EUV) lithography is used to print tight pitches in advanced logic, and imec notes that all leading logic manufacturers had announced EUV use for tight pitches. ASML reported EUV in high-volume production at 5 nm in its 2022 overview.
Do these 3 things before closing this tab:
1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minuteASML’s 2022 overview described High-NA EUV, with a numerical aperture of 0.55, as under development for single-exposure production around the 1 nm node. “Around the 1 nm node” is a roadmap target, not a claim that 1 nm chips were already in production in 2022. Lithography is one part of scaling: the transistor design, process integration, wiring and yield must work together.
Why wiring, power delivery and packaging matter too
As transistors shrink, signals and power still have to travel to and from them. Imec identifies source/drain contact resistance, routing congestion and resistance-capacitance (RC) delay in metal interconnects as major bottlenecks. If wires or contacts consume too much time or power, a smaller transistor cannot deliver its full potential at the chip level.
To address these constraints, imec’s roadmap evaluates conductors such as ruthenium and molybdenum, hybrid metallization, self-aligned gate contacts and buried power rails. It also discusses backside power delivery, which moves part of the power network to the back of the wafer, and advanced packaging, which can bring components and communication paths closer together. These techniques target system-level improvements and do not depend solely on shrinking the transistor.
Scaling also takes different forms in different kinds of chips. ASML reported that memory makers had produced 176-layer 3D NAND and announced roadmaps beyond 600 layers around 2030 in its 2022 overview. Those figures describe NAND layer counts, not logic-transistor counts or a guarantee that the announced roadmap will be met. They illustrate how vertical stacking can extend density even when simple planar shrinkage is no longer the whole story.
How to judge whether a new node is a real gain
A node label alone is not enough to compare chips or manufacturing generations. Compare the outcome across these dimensions:
Best Value
- Channel control and leakage: Does the gate control the channel effectively as dimensions shrink?
- Drive current and efficiency: Can the device deliver useful performance without an unacceptable power cost?
- Density and cell area: How much logic fits in a given area, including the standard-cell layout?
- Manufacturing complexity and yield: Can the architecture be produced consistently at volume?
- Interconnect and power delivery: Do contacts, wires and power networks keep pace with the devices?
- Cost and time to volume: Are the gains economically and operationally useful at high-volume manufacturing?
Transistor innovation remains central, but future gains depend on materials, device physics, topology and heterogeneous integration as well as lithography. That is the conclusion of a 2023 Nature review; it is also why claims about a new node should be evaluated across power, performance, area and cost together.
What you can try at home
A transistor assortment kit can help you learn the underlying circuit ideas by building simple switching or amplification experiments. Plusivo documents a kit containing 210 PNP and NPN BJTs with a resistor assortment and says it is available on Amazon. SparkFun’s discrete semiconductor kit includes N-channel MOSFETs and describes discrete semiconductors as basic building blocks of circuits. These are bench-top learning components, not tools for fabricating advanced-node chips: making those chips requires industrial lithography, deposition, etching, process control and packaging capabilities.
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
