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Build the counter as a synchronous modulo-1000 circuit: reset it to zero, increment it on a one-cycle clock-enable tick, and explicitly wrap 999 back to 0. A three-digit display adds decimal conversion or BCD counting, seven-segment decoding, and digit multiplexing. The oscillator frequency, reset polarity, display wiring, and FPGA pin assignments depend on your specific board.
Implement the modulo-1000 counter
A 10-bit register is wide enough to represent 0 through 999, but it can also represent 1000 through 1023. Add explicit wrap logic so those unwanted values are never reached during normal counting:
always @(posedge clk) begin
if (reset)
count <= 10'd0;
else if (tick) begin
if (count == 10'd999)
count <= 10'd0;
else
count <= count + 10'd1;
end
endHere, tick is a one-clock-cycle enable, not a separate, slow clock. With reset asserted, the counter loads zero; after reset is released, it advances only when tick is high. Its sequence is 0, 1, …, 998, 999, 0.
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Generate a visible count rate
FPGA board oscillators usually run too fast for a human to see each increment. Divide the input clock into a periodic enable pulse. If the board clock is Fclk and the desired count rate is Fcount, choose a divider terminal count near Fclk/Fcount - 1. Confirm the actual oscillator frequency and whether the board already conditions or divides that clock; the ratio alone does not identify a board’s clock setup.
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For example, a divider counter can count input-clock cycles, assert tick for one cycle at its terminal value, and return to zero. Keep the modulo-1000 state on the same trusted clock and use the pulse as an enable rather than using a fabric-generated ripple clock. For Spartan-6 clock resources and managed-clock options, consult AMD’s Spartan-6 FPGA Clocking Resources User Guide (UG382). A DCM or PLL-derived clock may be appropriate when the design already uses managed clocks, but adds clocking and timing considerations that a simple enable avoids.
Show 000–999 on three seven-segment digits
The counter value is binary; a three-digit display needs decimal digits. Two common approaches are:
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- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
| Approach | How it works | Trade-off |
|---|---|---|
| Binary counter with decimal conversion | Convert the binary count into hundreds, tens, and ones, then decode each decimal digit for the display. | Convenient when other logic needs a binary count, but requires conversion logic. |
| Three BCD digits with carry | Increment the ones digit; on 9, clear it and carry into tens; repeat the same rule from tens to hundreds. Wrap the hundreds digit after 9. | Digits are ready to display, but the design maintains decimal state rather than a binary count. |
For a typical multiplexed three-digit display, scan the digits with a faster refresh enable: select one digit at a time, place that digit’s segment pattern on the shared segment lines, then move to the next digit. The scan must be faster than the visible count update so the display can refresh while the number changes at a readable pace. The board’s circuitry determines the exact segment pattern, anode selection, and signal polarity.
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Do not copy pin numbers or display logic from another Spartan-6 board. Use the schematic, board guide, and constraints file for the exact board and FPGA part to identify:
- Oscillator frequency and clock input pin.
- Reset source and whether reset is active-high or active-low.
- Seven-segment line order and whether segment outputs are active-low.
- Anode or digit-select wiring and its active polarity.
- The exact XC6SLX device and package used by the design.
AMD’s Spartan-6 FPGA Packaging and Pinout Specifications (UG384) and Spartan-6 FPGA PCB Design Guide (UG524) provide device and implementation references, but the selected board’s own documentation and constraints determine its connections.
Verify behavior before programming the board
- Simulate reset: assert reset and confirm the count becomes zero.
- Check ordinary increments: confirm a count change occurs only on a one-cycle
tick. - Check both boundaries: test 998 to 999 and 999 to 0.
- Check display transitions: verify digit extraction or BCD carry at values such as 009 to 010 and 099 to 100.
- Build for the target: synthesize and implement for the exact XC6SLX part with the board’s constraints, then program and inspect the display.
If a pushbutton controls reset or counting, synchronize and debounce it before using it in the design; a mechanical button can produce multiple transitions, and an external button signal is not automatically aligned to the FPGA clock.
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- Arty S7 comes in two FPGA variants: Arty S7-25 features Xilinx XC7S25-CSGA324. Arty S7-50 features the larger Xilinx XC7S50-CSGA324.
- Internal clock speeds exceeding 450MHz
- On-chip analog-to-digital converter (XADC)
- Programmable over JTAG and Quad-SPI Flash
- Powered from USB or any 7V-15V source
Tool and device support
AMD’s Spartan-6 product page lists ISE resources and states that device support is extended until at least 2030. AMD also lists Spartan-6 evaluation platforms, including the Spartan-6 FPGA Connectivity Kit and SP605 Evaluation Kit. Check current AMD documentation and the board vendor’s materials for the tools, files, and hardware applicable to your setup.
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