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SiFive’s approach to AI is to license RISC-V processor IP that combines scalar, vector and matrix compute with software tuned for specific workloads. Its XM Series targets systems from edge devices to data centers; the SiFive Kernel Library (SKL) supplies optimized routines for using the hardware. These are components for chip designers and system builders—not consumer processors sold directly to individuals.
What SiFive’s AI strategy means
RISC-V is an open instruction-set architecture (ISA): a specification for the instructions a processor can execute. It is not itself a particular chip. SiFive designs and licenses processor IP based on RISC-V, which customers can incorporate into their own systems.
For AI, that means pairing different kinds of computation rather than relying on a CPU alone. Scalar cores handle general-purpose work; vector engines process many values in parallel; and matrix engines target the dense mathematical operations common in machine learning. Software libraries then help map workloads onto the available hardware.
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In a December 11, 2024 interview published by RISC-V International, SiFive senior director Ian Ferguson described AI as embedded across products rather than simply added as a standalone feature. He said customers need hardware flexibility because algorithms and their optimization requirements can change. Depending on the system, SiFive’s approach may use vector extensions to accelerate a CPU or a more substantial AI offload engine.
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What the XM Series is—and where it fits
The Intelligence XM Series is a licensable AI compute-engine IP family. SiFive introduced XM in a September 18, 2024 press release for applications including edge IoT, consumer devices, electric and autonomous vehicles, and data centers. Its AI/ML materials also position the family across those deployment settings. This describes intended application range, not a claim that one configuration suits every device or workload.
XM Gen 2 at a glance
| Published specification | SiFive’s stated figure or detail |
|---|---|
| Compute per cluster | Four integrated second-generation X300 cores |
| INT8 performance | 16 TOPS per GHz per cluster |
| BF16 performance | 8 TFLOPS per GHz per cluster |
| Memory bandwidth | 1 TB/s sustained per cluster |
| Compute elements | Scalar, vector and matrix engines; SiFive says Gen 2 adds new data types and is tuned for large language models |
| Host CPU options | RISC-V, x86, Arm, or no host CPU |
These are SiFive’s published specifications, not an independent benchmark or a guarantee of application throughput. The performance figures are stated per GHz, and the source does not provide a benchmark workload or test methodology for comparing them with another vendor’s product. Real results depend on implementation, clock rate, memory and system configuration, software, and the model being run.
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The host-CPU options matter for system design: XM is not limited to being paired with a SiFive host processor. A design may use a different host architecture, or no separate host CPU, depending on how the product is built.
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How SKL helps developers use the hardware
The SiFive Kernel Library is a tuned software suite for SiFive RISC-V vector and matrix engines. Its documented routines cover common building blocks for AI/ML and signal processing, including:
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- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
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- Matrix multiplication across multiple numeric types
- Depthwise convolution
- Nonlinear functions including exponential, softmax, SiLU and GELU
- Matrix transpose and packing for data movement and preparation
SKL integrates with SiFive’s Freedom SDK for Metal and Linux. SiFive has also announced an open-source reference implementation. That can give developers a starting point for adapting kernels, but it does not mean every part of SiFive’s processor IP or software stack is open source.
Optimized kernels can reduce the work required to map frequently used operations to specialized hardware. They do not remove the need to evaluate whether a model, numeric format, memory layout and target system are supported or efficient. The library’s value is therefore practical as well as architectural: software support is part of whether an AI engine can be used effectively.
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- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
From small devices to data centers: what “scale” means here
SiFive’s stated range runs from connected microcontrollers and consumer devices to autonomous vehicles and data centers. The same broad AI workload can impose very different constraints across those settings: a wake-word detector on an edge device has different power, memory and latency needs from a recommender system in a data center. A scalable IP family can let designers select and integrate compute suited to a product, but the published range alone does not establish performance, power consumption or cost for any particular deployment.
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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsThe RISC-V International interview describes use cases such as voice-assistant wake words, image recognition for autonomous driving and recommender systems. SiFive’s AI/ML materials also state that a large hyperscaler uses an X280 for AI data offload. The source does not identify that customer, so it should not be treated as a named deployment endorsement.
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- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
In the interview context, Ferguson said SiFive had more than 400 design wins and billions of chips deployed. Those are SiFive-reported company figures, not independently verified counts in the cited material; they also do not establish that all those designs or chips use XM or AI-specific hardware.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.SiFive and NASA’s space-computing project
NASA’s High Performance Spaceflight Computing (HPSC) project is a separate example of SiFive’s RISC-V technology in a demanding application. NASA’s SiFive announcement says the HPSC processor will use multiple SiFive X280 vector cores along with additional SiFive cores. SiFive says the processor is expected to deliver 100 times the computational capability of today’s space computers.
That 100× figure is an expectation attributed to SiFive, not a measured result reported in the announcement. The project’s described mission functions include autonomous rovers, vision processing, flight guidance and communications. HPSC is not identified as an XM Series deployment; the named SiFive core in the announcement is X280.
What to check when evaluating SiFive for an AI design
The published specifications are a starting point, not a complete selection guide. A design team comparing AI compute options should establish:
- Workload fit: whether the target model and its operations map to the scalar, vector and matrix capabilities available in the chosen configuration.
- Numeric format: whether INT8, BF16 or another supported type meets the model’s accuracy and throughput needs.
- Memory behavior: whether the system can make practical use of the stated bandwidth and keep the compute engines supplied with data.
- Software maturity: whether required kernels are available in SKL and integrate with the intended Freedom SDK, operating system and development flow.
- System integration: which host-CPU arrangement, interfaces and implementation choices suit the product.
- Measured results: performance per watt, latency and throughput on representative workloads. The cited SiFive materials do not provide an independent, like-for-like benchmark against named competitors.
How SiFive’s commercial model works
SiFive’s model for these products is processor-IP and software licensing, with contact-sales and download routes rather than a public consumer checkout. The cited materials do not state XM pricing. A company considering the IP would need to discuss licensing and implementation details with SiFive; an individual looking for a plug-in AI chip or a retail board should not assume XM is a directly purchasable product.
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