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Imec reported directly etched ruthenium (Ru) lines at 16 nm pitch using a semi-damascene process, with average resistance as low as 656 Ω/µm. The June 2025 announcement describes a research demonstration aimed at the M0 local-interconnect layer in future A7-and-later logic—not a production-ready chip process.
What the 16 nm-pitch result means
Pitch is the repeating spacing of neighboring features in a patterned structure; it is not the width of an individual Ru line. At this very tight pitch, imec’s reported average resistance reached as low as 656 Ω/µm. That is a line-resistance measurement, not a wafer-yield figure or a measure of total chip performance.
The result is notable because imec is investigating Ru direct etch as an alternative interconnect approach for pitches below 20 nm, where increasing resistance-capacitance (RC) delay is a concern for conventional copper (Cu) dual damascene. The announcement does not establish that Ru is superior across an entire interconnect stack.
How the semi-damascene process works
In the 2025 implementation, semi-damascene combines a modified EUV-based self-aligned double-patterning process called spacer-is-dielectric (SID) SADP with direct etching of Ru. Imec describes it as a two-level metallization module that begins by directly etching the first local-interconnect metal layer and could be extended to additional layers.
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In conventional dual damascene, metal is formed in dielectric trenches and vias, with chemical-mechanical polishing (CMP) used to remove excess metal. Imec’s general semi-damascene explainer describes a different sequence: form a via opening in dielectric, fill and overfill it with metal, then mask and etch the metal to define lines. The 2019 explainer gives background on the concept; it is not a complete recipe for the 2025 experiment.
Process choices imec credits for the result
Imec identifies three choices behind its 16 nm-pitch structures:
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- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
- Oxide- and nitride-based materials: Used for hard masks, spacers and gap fill.
- Pattern inversion and SiO₂ gap fill: A pattern-inversion step was paired with optimized silicon-dioxide (SiO₂) gap fill.
- Improved Ru etch: The etch was adjusted to minimize oxidation of the silicon-nitride (SiN) hard mask, which imec says helps avoid line-bridge defects.
Imec describes the flow as optimized for cost-effective manufacturability. The announcement provides no cost model or comparative cost data, so this is a stated design goal rather than a demonstrated cost advantage.
Read the resistance and yield figures separately
| Reported figure | What it describes |
|---|---|
| 656 Ω/µm | Imec’s reported lowest average resistance for the 16 nm-pitch Ru lines. |
| 40% | The share of 16 nm-pitch Ru line structures that met the resistance target predicted from thin-film resistivity. This is not a wafer-yield figure. |
| 90% and higher | Full-wafer yields imec cites for structures in the 18–22 nm pitch range, not for the 16 nm-pitch structures. |
These percentages describe different outcomes at different pitches: a target-meeting fraction for 16 nm-pitch structures versus full-wafer yield at 18–22 nm pitch. They should not be treated as directly comparable. The announcement does not provide an independent measurement dataset, sample count, error bars or measurement uncertainty for the headline result.
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Intended use—and what is not established
Imec positions the approach for M0, the first local-interconnect metal layer, in A7 and later logic technology nodes. Its June 3, 2025 release presents a research result and proposed technology path; it does not say the process is used in a commercial chip or qualified for volume production. Nor does it establish performance across a complete interconnect stack.
For conference context, the 2025 IEEE International Interconnect Technology Conference (IITC) program lists imec’s Gilles Delie presenting “MP16/18 integration in Ru semi-damascene using SiN-based core for spacer-is-dielectric SADP.” The program separately lists an IBM presentation titled “First demonstration of 16nm pitch subtractive Ru interconnects for advanced technology nodes.” Those entries do not show that the work used identical methods or make the results directly comparable. Imec’s release says the organization had 20 contributions at the conference; that event count is not a measure of independent technical validation.
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Imec’s view of the next steps
Seongho Park, imec’s nano-interconnect program director, said: “Now that industry is picking up Ru direct metal etch, imec is looking ahead to future generations and discusses further optimizations to its semi-damascene flow as well as new integration options.” This is Park’s characterization of industry activity and future work, not an independently verified adoption statistic.
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