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Etch is becoming more selective, more three-dimensional and more software-assisted because AI chips and memory must move and store vastly more data. Gate-all-around (GAA) logic needs controlled lateral removal at near-atomic precision, while 3D NAND requires deep, profile-preserving etches through hundreds of alternating films. At the same time, predictive models, virtual wafers and sensor data are changing how engineers develop and run those processes.
Why AI workloads are changing semiconductor etch
AI systems depend on parallel compute, high-bandwidth memory, dense non-volatile storage and fast movement of data between logic and memory. Those requirements are pushing manufacturers toward structures that are taller, more layered and less planar than earlier generations.
As device geometry moves into the third dimension, lithography alone no longer determines progress. Etch must define vertical holes, remove one film without attacking its neighbor, clean surfaces without damaging them and maintain the intended profile over extreme depths. Barrett Finch, senior director of Lam Research’s Etch Product Group, described the requirement in an EE Times article published November 6, 2023: advanced devices need selective removal, surface modification, higher aspect ratios and, in some cases, lateral rather than purely vertical etching.
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GAA logic turns etch sideways
Selective release of the channel
In a gate-all-around transistor, the gate must surround the channel rather than sit on only one side. A common fabrication sequence builds a multilayer stack, then selectively removes sacrificial material so the silicon channel is suspended and accessible from all directions.
This is fundamentally different from conventional anisotropic dry etch, which is optimized to remove material primarily from the top downward. The GAA release step must etch laterally and selectively while preserving the neighboring silicon. Small differences in chemistry, time or local loading can change the channel dimensions and the eventual electrical behavior of the transistor.
Angstrom-scale control and gentle surface treatment
Because the release changes surfaces that will become part of the transistor, process control must approach the angstrom scale. Engineers are balancing removal rate against selectivity, uniformity and damage rather than simply maximizing speed.
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Radical- or neutral-based etch can help when the goal is to remove native oxide, residual carbon or embedded impurities from an active GAA surface while modifying only an atomic-scale layer. These approaches reduce reliance on highly energetic ion bombardment during delicate cleaning steps, although the appropriate process window depends on the stack and integration scheme.
3D NAND moves the hardest etch into depth
Hundreds of films in one vertical path
3D NAND increases density mainly by stacking more oxide and nitride layers vertically. Channel holes and related features must pass through that stack, so the challenge is no longer just printing a small opening at the wafer surface. The opening must remain continuous, centered and correctly shaped all the way down.
Lam Research and Barrett Finch reported aspect ratios of 40:1 or more for these structures in 2023. The same account said a wafer can contain over one trillion channels. Both figures are source-reported scale indicators, not universal specifications for every 3D NAND generation.
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Maintaining a usable profile at extreme aspect ratio
As a feature gets deeper, reactants and by-products must travel farther, and ions reach the bottom with less useful energy. A process that etches quickly at the top can therefore taper, bow or develop other profile errors before reaching the bottom.
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Manufacturers are combining several controls:
- Ion-energy management: enough directional energy to sustain reaction at depth without eroding critical sidewalls.
- Wafer-temperature control: including cryogenic operation where a colder surface changes reaction rates, selectivity or by-product behavior.
- New chemistries: designed to improve the trade-off among etch rate, film selectivity and profile control.
- Power and process scaling: coordinated adjustments that keep conditions stable as stacks grow taller.
No single knob solves the problem. Increasing ion energy may improve bottom clearing but increase damage or sidewall loss; changing temperature or chemistry can improve selectivity while reducing throughput. The usable process is the one that keeps all of those effects inside the device’s electrical and manufacturing limits.
GAA and 3D NAND require different etch behavior
| Requirement | GAA logic | 3D NAND |
|---|---|---|
| Primary direction | Lateral, selective release around the channel | Predominantly vertical travel through a tall multilayer stack |
| Neighbor protection | Remove sacrificial material while preserving silicon | Maintain the intended response across alternating oxide and nitride films |
| Key precision problem | Angstrom-scale surface and channel control | Profile, uniformity and bottom clearing at extreme depth |
| Main damage concern | Surface or channel damage during release and cleaning | Sidewall erosion, bowing, taper and loss of etch capability at depth |
| Important process levers | Selectivity, gentle radicals or neutrals, tightly limited exposure | Ion energy, wafer temperature including cryogenic conditions, power and chemistry |
| Best development aid | Surface-sensitive modeling and measurements | Three-dimensional profile simulation, depth-sensitive metrology and chamber matching |
AI is entering etch-process development
Virtual wafers and three-dimensional simulation
Engineers can use predictive models to explore how a recipe will change a wafer surface or a three-dimensional structure before running every candidate on production equipment. Virtual-wafer and 3D simulations make it possible to test interactions among chemistry, power, temperature, geometry and film stack in software first.
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These models do not eliminate physical experiments. They narrow the search space, expose likely failure modes and help engineers choose experiments that are more informative than an unguided sweep of settings.
Sensor data and virtual metrology
Etch chambers generate time-series data from sensors as a process runs. When those signals are connected to calibrated models, a fab can estimate a wafer characteristic without measuring every wafer destructively. This is generally called virtual metrology.
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Chamber matching and fleet optimization
Production fabs operate multiple chambers that must deliver equivalent results. Data-driven matching helps engineers distinguish a recipe problem from equipment-to-equipment variation. Fleet-level optimization can then recommend settings or maintenance priorities across many tools instead of treating each chamber in isolation.
A reported “human first, computer last” workflow
Lam Research described a study in 2023 in which process engineers used AI assistance in a hybrid “human first, computer last” development model. The engineers set the problem and constraints; computation searched among millions of possible recipes and helped identify promising candidates. The report said this approach could cut development costs in half.
That figure is a finding reported from the Lam study, not a guaranteed saving for every process. In practice, engineers still have to verify candidate recipes on physical wafers, check reliability and confirm that the model remains valid when the stack, chamber or integration flow changes.
What an AI-era etch workflow has to optimize
- Directionality: whether the step must travel straight down, move laterally or combine both behaviors.
- Selectivity: how completely one material can be removed while adjacent films remain within tolerance.
- Profile control: whether the opening stays dimensionally correct from the top surface to its deepest point.
- Surface integrity: whether residues, native oxide and contamination are removed without creating electrical defects.
- Throughput and cost: whether the required precision can be delivered at an economically viable wafer-per-hour rate.
- Operating window: how much variation in temperature, power, pressure and chemistry the process can tolerate.
- Data integration: whether sensors, virtual metrology and predictive models can detect drift and guide action quickly.
What comes next for etch
The direction is not one replacement technology but a tighter combination of physics, chemistry, equipment control and computation. GAA pushes etch toward selective lateral release and gentle atomic-scale surface treatment. 3D NAND pushes it toward deeper, faster and more uniform vertical removal. AI tools add a second layer of capability by helping engineers simulate, search and control those processes.
As stacks grow and features shrink, the winning process will be the one that preserves a narrow profile and damage budget while remaining manufacturable across thousands of wafers and multiple chambers. The AI era therefore makes etch both a harder hardware problem and a richer data problem: advanced structures create the demand, and intelligent process development helps make them practical.
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