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Hardware virtual memory is the processor-supported system that translates the virtual addresses programs use into physical addresses in memory. The memory management unit (MMU) performs the translation using mappings configured by the operating system, helping keep each program’s address space separate from the machine’s physical memory layout.
What is hardware virtual memory?
Programs work with virtual addresses: addresses in their own logical address spaces. A physical address identifies a location in the computer’s memory system. Hardware virtual memory connects the two, so application code does not need to know where its data sits in physical memory. The Linux kernel describes the MMU as the hardware component that handles virtual-to-physical address translation (Linux Kernel Documentation: Page Tables).
This mechanism is not the same as saying that every virtual address is backed by a location in RAM at all times. A mapping may be absent, invalid, or refer to a page that is not currently resident in physical memory. The operating system determines how to handle those cases.
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- A program issues a virtual address. In a paged system, the address identifies a virtual page and an offset within that page.
- The MMU checks for a cached translation. The translation lookaside buffer (TLB) stores recently used translations. On a TLB hit, the processor can reuse the mapping without another page-table walk.
- On a TLB miss, the translation mechanism looks up the mapping. It consults the page tables, often through a multi-level page walk. Some architectures also cache information used during page walks.
- The physical address is formed. A valid mapping identifies a physical page frame; the original offset selects the location within that frame.
Page-table formats, lookup levels, page sizes, and translation stages vary by processor architecture. Arm’s AArch64 guide, for example, explains translation tables and translation stages for that architecture (Arm: Learn the architecture — AArch64 memory management Guide).
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What does the MMU do, and what does the operating system do?
The MMU is hardware that performs translation and can enforce access permissions and memory attributes. Page tables are data structures that describe address mappings; the operating system creates and changes them and handles faults when an access cannot proceed. The exact responsibilities and required operations depend on the architecture. Arm’s guide also covers software management of translation tables and TLB maintenance.
For a concrete, product-specific example, AMD’s Zynq-7000 technical reference manual describes an MMU with translation tables, a table walker, and a TLB. Its details apply to that system, not to every processor (AMD: MMU Functional Description).
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What happens when there is no usable mapping?
If an access lacks a usable mapping, violates permissions, or refers to a page not resident in physical memory, the processor raises a fault for the operating system to handle. Depending on the cause, the OS may make a page available and update mappings, or reject the access.
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A page fault is therefore not automatically a program error. It can be part of ordinary demand paging, where the operating system brings a needed page into memory. A fault caused by an invalid address or prohibited access may instead result in an error. The behavior depends on the operating system and the reason for the fault. Linux documents page tables and fault-related handling in its Page Tables documentation; Apple’s archived documentation explains the role of page faults in its virtual memory system (Apple: About the Virtual Memory System).
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Why use hardware virtual memory?
- Isolation: Processes can use separate logical address spaces, with access permissions helping prevent unauthorized access across mappings.
- Controlled sharing: The operating system can map selected memory for use by more than one process.
- Demand paging: A system can keep only needed pages in physical memory and arrange for software to handle accesses to pages that are not resident.
- Abstraction: Programs can use a logical address space without managing the physical memory layout themselves.
These capabilities describe the virtual-memory system as a whole: hardware performs address translation and permission checks, while the operating system manages mappings and policy. Linux’s overview discusses the abstraction, protection, sharing, and demand paging (Linux Kernel Documentation: Concepts overview).
Virtual address, physical address, MMU, and TLB at a glance
| Term | Meaning |
|---|---|
| Virtual address | An address used within a program’s logical address space. |
| Physical address | An address identifying a location in the machine’s memory system. |
| MMU | Processor hardware that translates addresses and can apply access permissions and memory attributes. |
| Page table | Operating-system-managed data describing mappings between virtual pages and physical page frames. |
| TLB | A cache of recent address translations that can avoid repeated page-table walks. |
| Page fault | A processor-raised event for an access the operating system must handle, such as a nonresident page or an invalid or prohibited access. |
What varies between systems?
The core idea is consistent—hardware translates addresses using mappings managed by software—but implementation details are architecture- and operating-system-dependent. Translation-table organization, supported page sizes, translation stages, TLB behavior and maintenance, permission checks, and fault handling can differ. Consult the official manual for the specific processor architecture when those implementation details matter.
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