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Global Unichip Corp. (GUC) announced on September 24, 2024 that a leading cloud service provider (CSP) and several high-performance computing (HPC) solution providers had adopted its 3nm HBM3E controller and physical-layer (PHY) IP. GUC did not identify any customer or chip. The related ASIC was forecast at the time to tape out during 2024 with HBM3E memory operating at 9.2Gbps.
What GUC actually announced
GUC said its 3nm HBM3E memory-controller and PHY IP had been adopted by one unnamed leading CSP and several unnamed HPC solution providers. The IP is intended for integration into custom ASICs that connect to high-bandwidth memory (HBM3E) in an advanced package; it is not an off-the-shelf computer component or memory module.
The announcement described the associated ASIC as “expected to tape out this year,” meaning 2024. That was a forecast made in September 2024, not a current prediction and not independent confirmation that the specific ASIC taped out.
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Which cloud provider adopted it?
GUC did not name the CSP. Its release also did not identify the HPC companies or the customer ASIC. Micron was mentioned as an HBM collaboration partner, but the announcement does not say that Micron was the adopting CSP. No customer identity should be inferred from that reference or from industry speculation.
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Capabilities GUC listed for the HBM3E IP
Process-node coverage
GUC reported readiness on TSMC N7/N6, N5/N4P and N3E/N3P technologies. The customer announcement specifically concerned a 3nm implementation.
HBM and package validation
The company said the IP had been silicon-validated with all major HBM vendors and on TSMC CoWoS-S and CoWoS-R packaging. GUC described eDTC for CoWoS-S and IPD for CoWoS-R as approaches intended to address power integrity.
Interposer routing and chiplet monitoring
GUC highlighted patented interposer routing that supports angle routing with a Y-dimension offset while maintaining signal and power integrity. It also said chiplet-interconnect monitoring was integrated into the HBM PHY through collaboration with proteanTecs.
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Optional multi-die design services
For customers building HBM-based CoWoS ASICs, GUC offered optional 2.5D and 3D multi-die design services. These are vendor-described design capabilities, not independent comparative test results.
What the 9.2Gbps figure means
GUC’s 9.2Gbps figure was the planned HBM3E memory data rate for the announced ASIC. It describes the 2024 design forecast and should not be read as a benchmark for a named production chip.
What later GUC reporting adds
| Report | Information provided | What it does not establish |
|---|---|---|
| FY2024 sustainability report | GUC said silicon validation was completed in 2024 for HBM3E PHY and controller IP with DRAM manufacturers’ 12Hi HBM3 and HBM3E. | It does not identify the CSP or tie validation to a particular customer ASIC. |
| April 23, 2026 HBM4 platform release | GUC said its previous-generation HBM3E PHY and controller had been deployed in customers’ 3nm products and had achieved production speeds 15% above specification. | This later company-reported status does not independently verify the unnamed CSP ASIC’s 2024 tape-out forecast. |
Why the announcement matters for data-center ASICs
HBM3E places very high-bandwidth memory beside logic in an advanced package. A custom accelerator therefore needs both a memory controller, which manages protocol and scheduling, and a PHY, which provides the electrical interface between the ASIC and HBM stacks. Interposer routing, power-integrity design and package validation are critical because the logic die, HBM devices and interposer must operate as one system.
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For an ASIC customer, the practical selection questions are the target process node, validated HBM supplier and stack configuration, CoWoS-S or CoWoS-R packaging, required memory rate, power-integrity approach and whether 2.5D or 3D design support is needed. GUC’s announcement supplies vendor claims along those axes but no independent customer-specific comparison.
Statements from the announcement
“We are thrilled to see our HBM3E Controller and PHY IP being integrated in CSP and HPC ASICs.”
“Memory is an integral part of AI servers and foundational to the performance and advancement of data center systems,”
Bottom line for readers
GUC announced adoption by an unnamed leading CSP and several HPC providers, not a named cloud company. The 2024 plan called for a 9.2Gbps HBM3E ASIC and a tape-out that year. Later GUC disclosures support broader silicon-validation and customer-deployment progress, including a 2026 claim of 15% production speed headroom, but they still do not reveal the original CSP or independently confirm that specific 2024 forecast.
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