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This Part 2 tutorial describes a historical software-build workflow for Alinx’s AXU2CGB Zynq UltraScale+ board: configure a PetaLinux 2021.2 project from the preceding hardware design, add GNU Radio 3.8 recipes, and build both a Linux image and SDK. It assumes you already have the XSA hardware description from Part 1; it is not a standalone board bring-up guide.
What Part 2 builds—and what it assumes
Matjaz Zibert’s March 30, 2022 Hackster.io tutorial targets PetaLinux 2021.2 and GNU Radio-related components at version 3.8. Its goal is to create a PetaLinux image and SDK for an AXU2CGB system, with recipes supplied through the META-SDR Yocto layer on the dpu-fpga branch.
The project depends on the FPGA hardware design from Part 1. That companion tutorial identifies the Vivado device part as xczu2cg-sfvc784-1-e and exports the XSA used to configure PetaLinux. Check that the XSA, board revision, and intended storage setup match your own hardware before applying the example settings. The Part 1 hardware-design tutorial covers the preceding step.
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GNU Radio components in the tutorial
The layer supplies these named components; gr-satellites is optional:
#1 Best Overall
- ARM plus FPGA Hybrid Architecture：Powered by AMD Xilinx Zynq UltraScale Plus XCZU15EG with ARM Cortex-A53 and FPGA logic, delivering powerful heterogeneous computing performance for embedded development.
- Large-Capacity DDR4 Memory：Equipped with 4GB DDR4 for ARM (PS) and 2GB DDR4 for FPGA (PL), ideal for high-speed data processing, real-time signal processing, and AI acceleration workloads.
- Rich High-Speed Interfaces：Includes FMC HPC, SFP, SATA, MIPI CSI, Mini DisplayPort, and 4K HDMI input and output. Perfect for image processing, video capture, and ultra-high bandwidth applications.
- Ideal for AI and Video Applications：Widely used in artificial intelligence, 4K video systems, edge computing, and deep learning inference. Supports DisplayPort interface for high-resolution display integration.
- Full Development Resources Included:Comes with schematics, Verilog HDL demos, and hands-on experiment guidelines. Supports fast prototyping for research, education, and product development.
- GNU Radio 3.8
- gr-osmosdr 3.8
- gr-fpga_ai 3.8
- gr-satellites 3.8 (optional)
The recipe names and versions describe the 2022 tutorial, not a verified set of currently maintained or compatible packages. The article directs readers to clone META-SDR into the PetaLinux project’s project-spec directory, check out dpu-fpga, add the layer as a user Yocto layer, and select the packages they need.
Historical PetaLinux 2021.2 workflow
The sequence below follows the tutorial’s configuration and build order. Exact menu wording and available options can vary by release; do not assume these 2021.2 instructions apply unchanged to a newer toolchain.
Rank #2
- All-in-One RFSoC Chip:Based on AMD Xilinx Zynq UltraScale+ RFSoC XCZU47DR, integrating ARM Cortex-A53, Cortex-R5, FPGA logic, and RF-class data converters in a single chip.
- High-Speed Analog Performance:Onboard 8-channel ADC (5Gsps) and 8-channel DAC (9.85Gsps), GPS clock input, VCXO, and external clock support for precision RF applications.
- Industrial-Grade Compute Core:Supports up to 930K logic cells, 4272 DSP slices, 425K LUTs, 38Mb BRAM, and wide-temperature operation (-40°C to +85°C), ideal for rugged environments.
- Comprehensive Interface Resources:Includes PCIe 3.0 x4, 100G QSFP28, 10G SFP, Gigabit Ethernet, USB 3.0, Mini DP, SD slot, M.2 SSD, CAN/RS485, JTAG/UART—ready for system-level integration.
- Flexible Storage and Expansion:Equipped with 8GB DDR4 for PS, 4GB DDR4 for PL, 32GB eMMC, dual QSPI Flash, 40-pin expansion port, and multiple startup modes for development flexibility.
- Create the project from the hardware export. From the software workspace, source the PetaLinux 2021.2 settings script, create a
zynqMPPetaLinux project, and configure it with the XSA generated in Part 1. - Set image packaging and boot arguments. Configure an EXT4 root filesystem for the tutorial’s SD/eMMC/QSPI/SATA/USB packaging choices, specify the SD partition device, and enter the tutorial’s kernel boot arguments. Its example includes a serial console,
root=/dev/mmcblk1p2, a read-write root mount, root wait, and a 512 MB CMA allocation. These are project-specific values, not universal AXU2CGB defaults; validate them against your board revision, storage wiring, and boot layout. - Adjust the user device tree. The tutorial configures the SD host’s write-protect and 1.8 V properties and enables USB host mode. Verify these settings against the matching Alinx manual and your actual hardware rather than copying them blindly. Alinx’s AXU2CGA/B User Manual is the manufacturer reference surfaced for the board family; use the documentation for your specific revision.
- Configure the kernel. The author disables CPU idle and CPU frequency scaling, sets library routine size to 1024 MB, and otherwise accepts defaults. These are the tutorial’s configuration choices, not general recommendations for performance, thermals, or power management.
- Add META-SDR and select packages. Clone the META-SDR repository into
project-spec, check outdpu-fpga, add it as a user Yocto layer, and enable the GNU Radio packages you intend to include. The tutorial also discusses OpenSSH options, package management, debug tweaks, and development packages for out-of-tree module work; include those only if they serve your build and deployment needs. - Build the image, then the SDK. Run
petalinux-build, inspect the generated files inimages/linux, and then runpetalinux-build --sdk. The tutorial estimates several hours for the image build and roughly an hour for the SDK build; these are its estimates, not measured guarantees for your machine.
What to verify before using the resulting image
A Zynq Linux deployment involves more than compiling GNU Radio. The GNU Radio Wiki’s Zynq setup overview describes the broader arrangement of Zynq hardware, FPGA design software, and an SD-card image containing the Linux kernel image, bootloader, root filesystem, and FPGA bitstream. That is general Zynq context, not validation of this AXU2CGB-specific tutorial.
- Confirm your exact AXU2CGB revision and that the XSA reflects the hardware design you intend to boot.
- Check that the root partition device in the boot arguments is correct for your storage and that the bootloader, kernel, root filesystem, and bitstream are packaged for that setup.
- Validate SD and USB device-tree properties against your board documentation and design.
- Keep the PetaLinux, GNU Radio, and META-SDR versions aligned with the historical workflow unless you have independently confirmed compatibility for another release.
Where the series goes next
Part 2 hands off the built Linux software platform to the later installments: Part 3 creates a Vitis platform and DPU application, and Part 4 builds an AI model using Colab and Vitis-AI. The series describes its broader target as AXU2CGA/B, while this Part 2 tutorial specifically focuses on AXU2CGB.
Quick Recap
Best Value
- Advanced Processing Power: Features Xilinx Zynq UltraScale+ ZU7EV SoC with quad-core ARM Cortex-A53, dual-core Cortex-R5, and Mali-400MP2 GPU for high-performance embedded applications.
- High-Speed Connectivity: Equipped with dual Gigabit Ethernet (PS & PL), PCIe 3.0 x4, dual SFP, USB 3.0 x4, and MIPI interface for versatile I/O expansion.
- Rich Multimedia Support: Offers HDMI 4K input/output, Mini DisplayPort, and 120/40Pin expansion headers for video and multimedia projects.
- Enhanced Storage & Boot Options: Supports NVMe SSD, dual SATA ports, onboard 8GB eMMC, and dual QSPI Flash for fast boot and data storage.
- Reliable Industrial-Grade Design: Operates from -40°C to +85°C with a robust layout, black matte PCB, and gold immersion finish; ideal for research, AI, and SDR prototyping.
Rank #4
- ARM plus FPGA Hybrid Architecture: Powered by AMD Xilinx Zynq UltraScale Plus XCZU15EG with ARM Cortex-A53 and FPGA logic, delivering powerful heterogeneous computing performance for embedded development.
- Large-Capacity DDR4 Memory：Equipped with 4GB DDR4 for ARM (PS) and 2GB DDR4 for FPGA (PL), ideal for high-speed data processing, real-time signal processing, and AI acceleration workloads.
- Rich High-Speed Interfaces: Includes FMC HPC, SFP, SATA, MIPI CSI, Mini DisplayPort, and 4K HDMI input and output. Perfect for image processing, video capture, and ultra-high bandwidth applications.
- Ideal for AI and Video Applications：Widely used in artificial intelligence, 4K video systems, edge computing, and deep learning inference. Supports DisplayPort interface for high-resolution display integration.
- Full Development Resources Included：Comes with schematics, Verilog HDL demos, and hands-on experiment guidelines. Supports fast prototyping for research, education, and product development.
Rank #3
- ARM plus FPGA Hybrid Architecture: Powered by AMD Xilinx Zynq UltraScale Plus XCZU15EG with ARM Cortex-A53 and FPGA logic, delivering powerful heterogeneous computing performance for embedded development.
- Large-Capacity DDR4 Memory：Equipped with 4GB DDR4 for ARM (PS) and 2GB DDR4 for FPGA (PL), ideal for high-speed data processing, real-time signal processing, and AI acceleration workloads.
- Rich High-Speed Interfaces：Includes FMC HPC, SFP, SATA, MIPI CSI, Mini DisplayPort, and 4K HDMI input and output. Perfect for image processing, video capture, and ultra-high bandwidth applications.
- Ideal for AI and Video Applications：Widely used in artificial intelligence, 4K video systems, edge computing, and deep learning inference. Supports DisplayPort interface for high-resolution display integration.
- Full Development Resources Included：Comes with schematics, Verilog HDL demos, and hands-on experiment guidelines. Supports fast prototyping for research, education, and product development.
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