Crashes, No Sound, or Screen Glitches?
Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteWindows Errors? Fix Them Before They Spread
Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstalliTechGuides is reader-supported. When you buy through links on our site, we may earn an affiliate commission. As an Amazon Associate I earn from qualifying purchases. Learn more
Flex Logix stopped selling its standalone InferX X1 AI accelerator chip and board and shifted to licensing the underlying InferX architecture as IP for integration into other companies’ SoCs. The change was a business-model pivot: CEO Geoff Tate said the market for chips and boards was relatively small, with too few large customers to make standalone sales attractive to a startup. InferX therefore remains relevant as licensable technology, not as a current consumer chip you can buy.
Why Flex Logix stopped selling the InferX X1
In May 2023, CEO Geoff Tate told EE Times that “the market for chips and boards was relatively small.” He said Flex Logix saw interest in automotive but that automotive was not a market a startup could readily sell into. Tate described the company’s conclusion as “the best way to take the technology market” being to “license everything that we built.”
The underlying issue was volume economics. Flex Logix judged that selling standalone accelerator chips and boards would not reach enough large customers, while licensing its technology could let multiple chipmakers and systems companies incorporate it into their own designs. This also aligned with the company’s existing eFPGA IP business.
What InferX IP is—and what it is not
InferX is an accelerator architecture intended for integration into a system-on-chip (SoC), rather than a single retail product. It combines multiply-accumulate (MAC) and tensor-processing hardware with reconfigurable interconnect. The specialized compute hardware is designed to perform efficiently, while the reconfigurable fabric can be adapted for different operations and workloads.
#1 Best Overall
![Arduino® UNO™ Q 4GB [ABX00173]- Hybrid Board, Qualcomm Dragonwing QRB2210 microprocessor (MPU) & STM32U585 Microcontroller(MCU), AI Vision, Voice, IoT, Robotics, Linux Debian OS, Wi-Fi 5, USB-C](https://m.media-amazon.com/images/I/51cl4xygwGL._SL160_.jpg)
- Dual-Brain Hybrid Power: Combines the Qualcomm Dragonwing QRB2210 MPU (Quad-core Arm Cortex-A53 @ 2.0 GHz CPU, Adreno GPU, AI acceleration) and the real-time, low-power STM32U585 MCU for advanced applications like object recognition, voice commands, and motion detection.
- AI & Linux Capabilities: Unlocks AI-powered vision and sound solutions; runs Linux Debian OS for coding in Python and supports the Arduino ecosystem with libraries and Sketches; quick start with Arduino App Lab.
- Advanced Features: Equipped with 4 GB LPDDR4 RAM, 32 GB eMMC built-in storage, ideal for single-board computer (SBC) mode, running multiple simultaneous high-level processes, more complex AI or ML models, extensive logs. Dual-band Wi-Fi 5 (2.4/5 GHz), Bluetooth 5.1, and high-speed headers for vision, audio, and display peripherals.
- Seamless Expansion & Connectivity: Features the classic UNO form factor for shields compatibility, an 8x13 LED matrix, and a Qwiic connector for easy expansion with Modulino nodes; power and connect via the USB-C connector.
- Intended Use & Development: The perfect platform for prototyping robotics or IoT projects, empowering innovators with a unified development experience to mix Arduino Sketches, Python scripts, and containerized AI models in a single interface.
Flex Logix’s 2023 positioning described the design as “80% hard-wired, but 100% reconfigurable.” That phrase describes the company’s architecture concept; it is not a standardized measure of performance or a guarantee that every part of a design can be reconfigured.
- It is not the InferX X1 board: the standalone chip-and-board sales ended.
- It is licensable IP: a chip designer can incorporate the architecture into a larger SoC rather than attach a separate accelerator.
- It is not simply a GPU or a general-purpose FPGA: InferX combines tensor/MAC processing with reconfigurable interconnect, occupying a different design point from either a conventional fixed-function accelerator or a fabric made predominantly of general-purpose FPGA logic.
How the AI and DSP software paths differ
The related hardware can support AI inference or digital signal processing (DSP), but the software path depends on the workload.
Rank #2
- Dual-Brain Hybrid Power: Combines the Qualcomm Dragonwing QRB2210 MPU (Quad-core Arm Cortex-A53 @ 2.0 GHz CPU, Adreno GPU, AI acceleration) and the real-time, low-power STM32U585 MCU for advanced applications like object recognition, voice commands, and motion detection.
- AI & Linux Capabilities: Unlocks AI-powered vision and sound solutions; runs Linux Debian OS for coding in Python and supports the Arduino ecosystem with libraries and Sketches; quick start with Arduino App Lab.
- Advanced Features: Equipped with 2 GB LPDDR4 RAM, 16 GB eMMC built-in storage, ideal to develop in PC-connected mode, running the OS, Python scripts, and basic network services (SSH) without a demanding GUI or heavy multitasking; great for lightweight AI and memory-optimized TinyML applications, needing local storage for basic OS and core libraries. Dual-band Wi-Fi 5 (2.4/5 GHz), Bluetooth 5.1, and high-speed headers for vision, audio, and display peripherals.
- Seamless Expansion & Connectivity: Features the classic UNO form factor for shields compatibility, an 8x13 LED matrix, and a Qwiic connector for easy expansion with Modulino nodes; power and connect via the USB-C connector.
- Intended Use & Development: The perfect platform for prototyping robotics or IoT projects, empowering innovators with a unified development experience to mix Arduino Sketches, Python scripts, and containerized AI models in a single interface.
AI inference
Flex Logix described an AI toolchain with quantization, graph compilation, operator compilation, and fabric configuration. These steps prepare a model and map its operations onto the hardware; fabric configuration is also intended to reduce traffic to external memory. Actual performance depends on the model, precision, implementation, process node, and system design.
The Tool Desk
Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →Digital signal processing
The DSP path supports configurable operations such as fast Fourier transforms (FFTs), finite impulse response (FIR) filtering, and matrix processing. Reconfiguration can adapt the implementation to different functions or FFT sizes. In a March 2024 announcement, Flex Logix described InferX DSP as a soft-IP 128-INT16-MAC tensor processor for EFLX eFPGA implementations spanning 40 nm to 7 nm.
Rank #3
- Single core ARM Cortex-A7 32-bit core, integrated with NEON and FPU
- Built in Micro's self-developed 4th generation NPU, with high computational accuracy and support for mixed quantization of int4, int8, and int16. Among them, int8 has a computing power of 0.5 TOPS and int4 has a computing power of up to 1.0 TOPS
- Built in self-developed 3rd generation ISP3.2, supports 4 million pixels, and supports various image enhancement and correction algorithms such as HDR, WDR, and multi-level denoisin
- It has powerful encoding performance, supports intelligent encoding, adapts to save bit rates according to the scene, and saves more than 50% of the bit rate compared to conventional CBR mode, making the captured images high-definition, smaller in size, and doubling the storage space
- The design with built-in RISC-V MCU supports low-power fast startup, 250ms fast capture, and simultaneous loading of AI model library, enabling facial recognition to be completed within 1 second
What the reported performance figures mean
The available figures describe different configurations, precisions, and evidence types. They should not be treated as a direct benchmark comparison: TOPS measures operations per second under a stated numeric format, whereas an inference-per-second result is tied to a particular model and configuration.
| Reported figure | Configuration and qualification | Source and date |
|---|---|---|
| 4 TOPS INT16 per tile; 1 TOPS for complex INT16 per tile | TSMC N5 at 1 GHz; the report gives the figures per compute tile. | EE Times, 2023 |
| 175 YOLOv5-S inferences per second | Two compute tiles in TSMC N7; tied to the stated YOLOv5-S workload and configuration. | EE Times, 2023 |
| 16 INT8 TOPS at 1 GHz and approximately 1 W per tile | A 5 nm target described by TechInsights; these are reported targets, not an independent benchmark result. | TechInsights, September 8, 2026 |
The 2023 N5 INT16 figure, the N7 YOLOv5-S result, and the 2026 N5 INT8 target differ in precision, process, and measurement type. They do not establish a like-for-like comparison with a GPU, another accelerator, or one another. A prospective licensee would need workload-specific performance, power, and silicon-area data for its intended implementation.
Rank #4
- 【POWERFUL ESP32‑S3 CONTROLLER】Built‑in Xtensa 32‑bit LX7 dual‑core processor, 512KB SRAM, 8MB PSRAM, 16MB Flash for stable AI voice computing and multitask processing.
- 【Preloaded Dual AI Platforms】Comespre-installed with complete Deepseek and OpenAI voice dialogue projects.Experience intelligent voice interaction instantly. (Note: OpenAI functionality requires your own API key.)
- 【STABLE WIRELESS & CLEAR AUDIO】Integrated 2.4GHz Wi‑Fi + Bluetooth 5 (LE); dedicated audio decoding module for natural, responsive voice interaction.
- 【USER‑FRIENDLY VISUAL & PLUG‑AND‑PLAY】2” TFT‑SPI color screen shows real‑time chat; modular design, no extra wiring, ready to use after setup.
- 【FULL LEARNING SUPPORT】45 programmable GPIOs, rich interfaces, online web tutorials, free technical support for beginners & developers.
How InferX differs from GPUs and conventional FPGAs
The useful comparison is not a single TOPS number. InferX’s stated design point is specialized tensor/MAC processing combined with reconfigurable interconnect, offered as IP for on-chip integration. A GPU is a separate accelerator architecture; a conventional FPGA offers reconfigurable logic fabric. Which approach fits depends on how much flexibility the workload needs, where computation sits in the system, and the efficiency achieved in a specific implementation.
Quick wins for a faster PC:
Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →| Decision factor | InferX IP | Questions to ask of a GPU or FPGA alternative |
|---|---|---|
| Business model and integration | Licensed IP intended for integration into a customer’s SoC. | Is the option a standalone accelerator, a board, or IP integrated on-chip? |
| Workload | Related hardware and software paths target AI inference and DSP. | Does the alternative support the required AI models, DSP functions, or both? |
| Reconfigurability | Tensor/MAC hardware with reconfigurable interconnect. | How much is fixed-function, and how much can be changed after design or deployment? |
| Efficiency | Must be evaluated for the target process, configuration, precision, and workload. | Compare performance per watt and per area under the same conditions, not headline peak figures alone. |
| Software | AI uses quantization and graph/operator compilation; DSP supports configurable signal-processing operations. | Can the toolchain map the actual model or signal-processing pipeline, and what engineering effort is required? |
| Commercial scale | Licensing is aimed at chip and SoC designers, with economics tied to design wins and integration. | Can the supplier support the expected volumes, design cycle, and product lifetime? |
Who InferX is for
The intended audience is semiconductor and system designers evaluating IP for custom chips—not ordinary consumers looking to purchase an X1 accelerator. Flex Logix joined Intel Foundry’s Accelerator IP Alliance on February 12, 2024, an ecosystem route to reach foundry customers. That alliance is not evidence of a consumer product launch or a public self-service licensing offer.
TechInsights reported on September 8, 2026, that Flex Logix had ceased chip-building operations and was offering InferX tiles as IP. The practical next step for an interested company is a direct commercial and technical discussion with Flex Logix about licensing, supported process options, software access, implementation support, and current availability. Public sources cited here do not establish a public licensing price or a self-serve purchase path.
Quick Recap
InferX timeline
| Date | Development |
|---|---|
| April 24, 2023 | Flex Logix announced InferX IP and software for DSP and AI inference. |
| May 8, 2023 | EE Times reported that Flex Logix had stopped selling InferX X1 chips and would license the architecture instead. |
| February 12, 2024 | Flex Logix joined Intel Foundry’s Accelerator IP Alliance. |
| March 6, 2024 | Flex Logix announced InferX DSP development for EFLX eFPGA implementations from 40 nm to 7 nm. |
| September 8, 2026 | TechInsights reported that Flex Logix had ceased chip-building operations and was offering InferX tiles as IP. |
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
