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Femtosense’s AI-ADAM-100 is an audio-focused system-in-package (SiP) that pairs the company’s SPU-001 sparse-AI accelerator with an ABOV Semiconductor Arm Cortex-M0+ microcontroller. It is designed to handle voice processing locally in products such as earbuds, hearing aids, remote controls and home appliances, rather than sending every audio task to the cloud. Femtosense said engineering samples were available in July 2024; the cited material does not establish the product’s current production status or purchasing channel.
What the AI-ADAM-100 is
The AI-ADAM-100 combines two chiplets in one package: Femtosense’s SPU-001, a sparse-AI processor for audio and other time-series sensor data, and an ABOV Semiconductor microcontroller. The companies presented the SiP as a low-cost, low-power option for voice control in consumer electronics and white goods.
Its intended role is to run voice tasks on the device. Femtosense’s July 17, 2024 announcement describes on-device voice processing and voice cleanup, with local processing intended to reduce response latency, power use, audio sent to cloud services and backend infrastructure load. These are the company’s stated benefits, not results from a published comparison against a named competing product.
How the chiplet-plus-MCU design works
SPU-001 handles AI workloads
EE Times describes the SPU as having two cores, each with four independent 16-way parallel vector-processing ALUs, and 1 MB of SRAM. The reported precision options are INT16 activations with INT8 weights, INT8 activations with INT8 weights, and INT8 activations with INT4 weights. Lower-precision weights and sparsity are part of the design’s approach to fitting AI workloads into a compact, power-conscious device.
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- Dual-Brain Hybrid Power: Combines the Qualcomm Dragonwing QRB2210 MPU (Quad-core Arm Cortex-A53 @ 2.0 GHz CPU, Adreno GPU, AI acceleration) and the real-time, low-power STM32U585 MCU for advanced applications like object recognition, voice commands, and motion detection.
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EE Times reported Femtosense’s figure of 500 GOPS/W for raw computational efficiency at 200 MHz with INT4 weights and INT8 activations. It also reported 50 TOPS/W effective efficiency at maximum sparsity. These are different reported measures and conditions; neither is a like-for-like benchmark against another chip.
ABOV’s MCU provides control
eeNews Europe describes the ABOV controller as a 40 nm Arm Cortex-M0+ MCU with 8 KB of SRAM and 32 KB of embedded flash. EE Times identifies the MCU family but does not independently verify each memory figure. In the combined design, the MCU supplies a general-purpose control component alongside the specialized SPU rather than requiring the AI accelerator to serve as the whole system controller.
Why put the parts in a SiP
Femtosense CEO Sam Fok told EE Times that the company can pair its SPU with different MCUs in ABOV’s portfolio without redesigning a complete system-on-chip each time. The approach can also accommodate chiplets built on different process nodes. That matters because embedded flash and dense AI memory may not be available on the same process node. A SiP can therefore give a product designer more flexibility than a single monolithic chip, though the cited sources do not quantify any resulting cost or schedule savings.
Rank #2
- Dual-Brain Hybrid Power: Combines the Qualcomm Dragonwing QRB2210 MPU (Quad-core Arm Cortex-A53 @ 2.0 GHz CPU, Adreno GPU, AI acceleration) and the real-time, low-power STM32U585 MCU for advanced applications like object recognition, voice commands, and motion detection.
- AI & Linux Capabilities: Unlocks AI-powered vision and sound solutions; runs Linux Debian OS for coding in Python and supports the Arduino ecosystem with libraries and Sketches; quick start with Arduino App Lab.
- Advanced Features: Equipped with 2 GB LPDDR4 RAM, 16 GB eMMC built-in storage, ideal to develop in PC-connected mode, running the OS, Python scripts, and basic network services (SSH) without a demanding GUI or heavy multitasking; great for lightweight AI and memory-optimized TinyML applications, needing local storage for basic OS and core libraries. Dual-band Wi-Fi 5 (2.4/5 GHz), Bluetooth 5.1, and high-speed headers for vision, audio, and display peripherals.
- Seamless Expansion & Connectivity: Features the classic UNO form factor for shields compatibility, an 8x13 LED matrix, and a Qwiic connector for easy expansion with Modulino nodes; power and connect via the USB-C connector.
- Intended Use & Development: The perfect platform for prototyping robotics or IoT projects, empowering innovators with a unified development experience to mix Arduino Sketches, Python scripts, and containerized AI models in a single interface.
What it could be used for
Femtosense and ABOV named true wireless stereo (TWS) earbuds, headsets, hearing aids, remote controls and home appliances as target categories in their December 2023 collaboration announcement. The common fit is a product that needs to listen for a wake phrase, clean up voice audio or respond to spoken commands while keeping its main controller or connectivity module asleep until needed.
- Earbuds and headsets: local voice processing or voice cleanup in a compact audio product.
- Hearing aids: a possible category for embedded audio AI. A separate femtoAI announcement in March 2025 describes NewSound OTC hearing aids using Clara AI speech enhancement; that implementation is not evidence that the hearing aids use the AI-ADAM-100.
- Remote controls and appliances: wake-word detection or spoken appliance control without relying on continuous cloud inference.
The March 2025 femtoAI announcement reported 7–13 dB of background-noise suppression across a broad range of environments and all-day operation on a single charge for the named NewSound/Clara implementation. Those figures describe that implementation, not the AI-ADAM-100 itself.
How it compares with other design approaches
The available reports do not provide controlled, like-for-like tests against a named MCU, audio DSP/NPU or application processor. The table below therefore compares the design choices conceptually, not measured performance.
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- Single core ARM Cortex-A7 32-bit core, integrated with NEON and FPU
- Built in Micro's self-developed 4th generation NPU, with high computational accuracy and support for mixed quantization of int4, int8, and int16. Among them, int8 has a computing power of 0.5 TOPS and int4 has a computing power of up to 1.0 TOPS
- Built in self-developed 3rd generation ISP3.2, supports 4 million pixels, and supports various image enhancement and correction algorithms such as HDR, WDR, and multi-level denoisin
- It has powerful encoding performance, supports intelligent encoding, adapts to save bit rates according to the scene, and saves more than 50% of the bit rate compared to conventional CBR mode, making the captured images high-definition, smaller in size, and doubling the storage space
- The design with built-in RISC-V MCU supports low-power fast startup, 250ms fast capture, and simultaneous loading of AI model library, enabling facial recognition to be completed within 1 second
| Approach | What runs the audio AI | What can be concluded from the cited material |
|---|---|---|
| AI-ADAM-100 SiP | SPU-001 accelerator paired with an ABOV Cortex-M0+ MCU | Designed for local voice and audio processing. Reported SPU efficiency figures and architecture are described above; no named-product comparison is provided. |
| Conventional MCU with cloud inference | The device captures or preprocesses audio; inference may be handled remotely | Femtosense presents local processing as a way to reduce latency, power use, cloud data transfer and backend load. The cited sources give no measured comparison or quantified cloud-data reduction. |
| MCU plus separate audio DSP or NPU | A separate audio or AI processor works alongside the MCU | The cited material does not name a competing device or establish comparative performance, memory needs, bill of materials or software effort. |
| Larger application processor | A more general-purpose processor handles system and AI workloads | The cited material supplies no direct comparison for power, latency, cost, package constraints or model capacity. |
For an engineering decision, the headline efficiency figures are not enough on their own. A team would also need to check its model’s memory footprint and accuracy at the supported precisions, always-on power, microphone and audio-path requirements, software workflow, package and MCU options, and the supplier’s current support and availability.
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The SPU’s reported 1 MB of SRAM is a relevant constraint for embedded inference, but model size alone does not determine whether a workload will fit or perform acceptably. EE Times reported a customer example in which workloads requiring about 7 MB of memory ran in the SPU’s 1 MB SRAM with acceptable quality. That is a reported customer result, not an independently reproduced benchmark or a guarantee for other models.
The same EE Times account says sparsity can allow multiple models to run at once. In practice, engineers would need to evaluate their own models and quality targets: the sources do not specify which workloads, sparsity levels or accuracy thresholds produced the reported customer result.
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- 【FULL LEARNING SUPPORT】45 programmable GPIOs, rich interfaces, online web tutorials, free technical support for beginners & developers.
Can engineers buy or evaluate it?
Femtosense’s July 17, 2024 release said engineering samples were available then, with commercial mass production targeted for later that year. It also listed software tools, evaluation boards and demonstration AI models, including a Smart Home Appliance Wake-up and Control model. That announcement establishes what the company offered or planned at the time; it does not confirm present-day stock, mass-production status or an active public evaluation program.
As of September 30, 2026, the cited material does not establish current production volume, distributor inventory, pricing, package variants or a public developer-program signup route. Engineers interested in evaluation should verify availability and support directly with femtoAI or ABOV, asking specifically about the AI-ADAM-100 evaluation board, SDK, supported demo models, sample terms and authorized sales channel.
Company naming and product context
The AI-ADAM-100 materials originally used the Femtosense name. The company’s press-release index records that “Femtosense is now femtoAI” in an item dated June 26, 2025, so current company references may use femtoAI.
Femtosense CEO Sam Fok called the AI-ADAM-100 the first device on the market to fully unlock sparse AI’s advantages. That is the company’s characterization; the cited reports do not establish a market-wide comparison. ABOV CEO Choi Won described it as an optimized AI MCU solution for voice and audio applications, also a company claim rather than an independent evaluation.
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