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Build a split-core Zynq UltraScale+ example by giving the Cortex-A53 and Cortex-R5-0 separate AXI GPIO peripherals and separate applications: FreeRTOS runs on the A53, while standalone firmware runs on the R5. In the ZCU104 walkthrough, each core polls its own pushbutton and toggles its own programmable-logic-connected LED. The key adaptation work is assigning board-correct I/O pins and ensuring the applications’ DDR linker regions do not overlap.
What the dual-core example does
The Hackster.io tutorial by FPGAPS, published December 11, 2024, uses a ZCU104 evaluation board to demonstrate two applications running on different processing-system cores while controlling distinct PL peripherals. The design contains four AXI GPIO instances: an output and an input assigned to the A53 application, and another output and input assigned to the R5 application.
Each program polls its assigned button. When pressed, it toggles its assigned LED and prints a core-specific “Hello world” message; a delay makes the LED behavior visible. The tutorial identifies DS40 and SW18 for the A53 side, and DS39 and SW17 for the R5 side. These identifiers and the corresponding pin assignments apply to the ZCU104 example, not automatically to other boards.
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| Core | Software environment | PL resources | Behavior |
|---|---|---|---|
| Cortex-A53 | FreeRTOS | Its own AXI GPIO output and input | Polls its button, toggles its LED, and prints its core-specific message |
| Cortex-R5-0 | Standalone | Its own AXI GPIO output and input | Polls its button, toggles its LED, and prints its core-specific message |
The GPIO blocks connect through AXI infrastructure to a high-performance master path from the processing system. Each application uses memory-mapped accesses to the base addresses for its own GPIO instances. Separate peripherals give the applications clear ownership of their I/O; they do not, by themselves, solve shared-memory or linker-layout concerns.
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Build the hardware platform in Vivado
- Add four AXI GPIO peripherals: two configured for the LED outputs and two for the button inputs. Connect them into the design’s AXI infrastructure and processing-system path.
- Expose and name the PL I/O ports, connect the design, validate it, and assign addresses. Select pin constraints for the actual board. The tutorial supplies a ZCU104 XDC for its example; other boards require their own appropriate documentation or board files.
- Generate the bitstream and export the hardware platform (XSA) for Vitis.
Create the A53 and R5 applications in Vitis
- Create the A53 application and domain using FreeRTOS, along with the Zynq MP FSBL boot component described in the tutorial.
- Add a domain for Cortex-R5-0 using the standalone OS, then create the R5 application against that domain.
- Use the generated platform address definitions so each application accesses the base addresses of its assigned AXI GPIO instances.
The tutorial describes a workflow using Vivado for hardware design and Vitis for the software platform and applications. Tool labels and availability can vary by release, so use the options offered by the version installed for the exported platform rather than assuming the walkthrough is release-independent.
Prevent the applications’ DDR regions from overlapping
Review both linker scripts before building. The tutorial warns that default linker settings may place both applications in overlapping DDR regions. Its example assigns 1 GiB per core, with the R5 retaining a base of 0x100000 and the A53 starting after the R5 range.
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Those values are the tutorial author’s example, not a universal memory map. Determine the available DDR range and any reserved regions for the exported hardware platform, then choose non-overlapping regions large enough for each application and its runtime needs. Confirm the resulting linker settings against the platform you actually built; the tutorial does not establish that its exact addresses apply to every configuration or tool release.
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Build and launch both applications
- Build the hardware platform and both core-specific applications.
- Connect the target board for the tutorial’s JTAG and UART-based launch flow.
- Use the hardware launch flow to program the PL and load both applications.
- Check the UART console for the separate messages, then press each assigned button and observe its associated LED.
FPGAPS reports seeing separate console messages and the expected I/O behavior on the ZCU104. That is the tutorial author’s reported result, not an independently reproduced test.
Rank #3
- ARM plus FPGA Hybrid Architecture: Powered by AMD Xilinx Zynq UltraScale Plus XCZU15EG with ARM Cortex-A53 and FPGA logic, delivering powerful heterogeneous computing performance for embedded development.
- Large-Capacity DDR4 Memory：Equipped with 4GB DDR4 for ARM (PS) and 2GB DDR4 for FPGA (PL), ideal for high-speed data processing, real-time signal processing, and AI acceleration workloads.
- Rich High-Speed Interfaces：Includes FMC HPC, SFP, SATA, MIPI CSI, Mini DisplayPort, and 4K HDMI input and output. Perfect for image processing, video capture, and ultra-high bandwidth applications.
- Ideal for AI and Video Applications：Widely used in artificial intelligence, 4K video systems, edge computing, and deep learning inference. Supports DisplayPort interface for high-resolution display integration.
- Full Development Resources Included：Comes with schematics, Verilog HDL demos, and hands-on experiment guidelines. Supports fast prototyping for research, education, and product development.
What to adapt for another board
- Physical I/O: Replace the ZCU104-specific LED and button identifiers, pin constraints, and XDC assignments with those supported by the target board.
- Hardware address map: Use the addresses generated for your exported platform, not copied constants from a different design.
- Memory layout: Allocate and verify non-overlapping linker regions using your platform’s real DDR map and reservations.
- Runtime setup: Preserve the intended software split—FreeRTOS on A53 and standalone on R5—only if it matches your project’s requirements and platform configuration.
Read the FPGAPS tutorial on Hackster.io for its original project steps and ZCU104 example files.
Quick Recap
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Rank #4
- ARM plus FPGA Hybrid Architecture: Powered by AMD Xilinx Zynq UltraScale Plus XCZU15EG with ARM Cortex-A53 and FPGA logic, delivering powerful heterogeneous computing performance for embedded development.
- Large-Capacity DDR4 Memory：Equipped with 4GB DDR4 for ARM (PS) and 2GB DDR4 for FPGA (PL), ideal for high-speed data processing, real-time signal processing, and AI acceleration workloads.
- Rich High-Speed Interfaces: Includes FMC HPC, SFP, SATA, MIPI CSI, Mini DisplayPort, and 4K HDMI input and output. Perfect for image processing, video capture, and ultra-high bandwidth applications.
- Ideal for AI and Video Applications：Widely used in artificial intelligence, 4K video systems, edge computing, and deep learning inference. Supports DisplayPort interface for high-resolution display integration.
- Full Development Resources Included：Comes with schematics, Verilog HDL demos, and hands-on experiment guidelines. Supports fast prototyping for research, education, and product development.
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