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A multi-gigabit SerDes is almost always a mixed-signal design, not a choice between an all-analog and an all-digital link. Keep the electrical interface and continuous-time functions—such as the output driver, receiver front end, and clock-generation elements—in analog circuitry. Use digital circuitry for adaptation, calibration, monitoring, clock-and-data-recovery control, and sampled-data equalization when the required reach, BER, power, and latency justify its cost. The right boundary depends chiefly on channel loss, lane rate, reliability target, process and power budgets, and whether an ADC-based receiver is practical.
What “analog vs. digital” means in a SerDes
A SerDes converts parallel data into a high-speed serial stream at the transmitter and reconstructs data at the receiver. The channel between them—such as a cable, connector, package, or circuit-board trace—attenuates and distorts the signal. At multi-gigabit rates, a useful design has to manage that electrical channel as well as the logic that encodes, recovers, and adapts the data.
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In an analog implementation, continuous electrical signals are shaped and processed by circuits such as drivers, termination, gain stages, continuous-time linear equalizers (CTLEs), and clock-generation blocks. Digital processing operates on logic values or sampled representations of the signal. Examples include clock-and-data-recovery (CDR) algorithms, calibration, monitoring, and feed-forward or decision-feedback equalization (FFE and DFE). An ADC-based receiver samples the incoming waveform so more of its equalization and adaptation can happen digitally, but the ADC and its analog input circuitry are still part of the system.
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Where the analog/digital boundary usually goes
| Function | Typical implementation | Why it fits there |
|---|---|---|
| Transmitter output driver and termination | Analog | They directly drive and match the electrical channel. |
| Receiver gain and continuous-time equalization | Analog | They condition the incoming waveform before any sampling decision. |
| PLL, VCO, or DCO clock-generation elements | Analog, digital, or hybrid, depending on architecture | Clock generation is a physical timing function, while its control and loop implementation can use digital components. |
| CDR control and adaptation | Often digital or hybrid | Algorithms can adjust timing and equalization settings to operating conditions. |
| FFE/DFE, calibration, monitoring, lane deskew, and presets | Often digital, with analog support where needed | Programmable logic supports adjustable tap weights, diagnostics, and adaptation. |
| ADC-based waveform sampling | Mixed-signal | The ADC converts a conditioned analog input into samples for digital equalization and other processing. |
These are typical placements, not a rule that every design must follow. For example, a CDR need not use a conventional analog loop filter and VCO arrangement: an IEEE Journal of Solid-State Circuits paper in 2006 analyzed replacing those elements in a PLL-based CDR with digital components, including the effects of jitter and limit-cycle behavior.
What each approach buys—and what it costs
Analog processing
- Strengths: Continuous-time equalization and gain can correct a signal before it reaches an ADC. An analog equalizer avoids the sampling and quantization power of an ADC and can provide low-latency correction.
- Costs: Analog behavior varies with process, voltage, temperature, component mismatch, supply and substrate noise, and calibration accuracy. Analog clock-generation and CDR circuits also need careful isolation from switching logic.
- Good fit: Use analog where continuous-time bandwidth, low noise, and a low-latency electrical response matter more than highly flexible post-sampling processing.
Digital processing
- Strengths: Digital equalization and CDR can provide programmable tap weights, adaptation, diagnostics, and portability across channels or standards. Digital controls can also make calibration and monitoring more systematic.
- Costs: Digital logic consumes clocking and switching power and can add latency. At very high rates, ADC-based approaches may need costly sampling, time interleaving, calibration, and mismatch correction.
- Good fit: Use digital where the value of adaptation, programmability, and algorithmic flexibility outweighs the power, area, latency, and conversion costs.
Neither choice removes noise or channel loss. A 2003 EE Times comparison described an important distinction: analog circuits process noise along with the signal, while digital circuits mainly turn noise into timing variation bounded by logic noise margins. That distinction is a useful way to think about the boundary, not a guarantee that digital processing will recover any signal or that analog circuitry is inherently noisier.
Can digital equalization replace analog equalization?
Not completely. A digital equalizer can correct sampled data, but it cannot make a badly attenuated or distorted input harmless before the receiver has acquired and sampled it. ADC-based receivers still require an analog front end, and the ADC brings its own quantization, integral and differential nonlinearity, and time-interleaving mismatch concerns. A 2019 IEEE Transactions on Components, Packaging and Manufacturing Technology article identifies those as key considerations in ADC-based receiver design.
Analog and digital equalization can work together: analog conditioning handles the continuous-time input, while digital FFE or DFE addresses remaining intersymbol interference (ISI) in the samples. Transmitter pre-emphasis is another part of the same strategy. Analog Devices explains that transmitter pre-emphasis and receiver equalization can compensate for frequency-dependent cable loss and help recover degraded data over extended or inexpensive cables. The goal is not to declare one equalizer type superior; it is to ensure the complete transmit-channel-receive path meets its target.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What published SerDes examples show
Published designs show that the balance changes with data rate and architecture. Their reported measurements are useful evidence that particular approaches can work under stated conditions; they are not apples-to-apples benchmarks. The studies use different rates, channels, BER targets, and power accounting.
| Published design | Architecture and reported result | How to interpret it |
|---|---|---|
| IBM/IEEE Journal of Solid-State Circuits, 2005 | A 4.9–6.4 Gb/s CMOS SerDes used a four-tap transmitter FFE and a five-tap receiver DFE. It reported 35 ps peak-to-peak total jitter at 10-12 BER, operation over more than 32 dB of channel loss at Nyquist, and 290 mW for the transmitter/receiver pair with amortized PLL power. | A mixed transmitter/receiver equalization strategy was reported to operate over a high-loss channel at the stated rate and BER. The 290 mW figure includes amortized PLL power for the pair; it is not a per-bit or per-lane figure stated independently of that design. |
| IEEE Journal of Solid-State Circuits, 2020 | A 112 Gb/s PAM4 receiver used a resonant analog front end, 64-way ADC, 16-tap digital FFE, one-tap DFE, and a 7 GHz DCO. It supported a −35 dB Nyquist channel at 10-6 pre-FEC BER. | The design combined analog input processing with substantial sampled-data equalization. Its BER is specified before forward error correction (FEC), so it should not be compared directly with a post-FEC target. |
| IEEE Journal of Solid-State Circuits, 2023 | A 224 Gb/s PAM4 receiver in 5 nm used a hybrid analog front end, a 64-way time-interleaved ADC, up to 30 digital FFE taps, optional DFE, and a 14 GHz digitally controlled oscillator. Reported analog power was 1.41 pJ/b. | The reported power is for the analog portion, not the total receiver. The architecture illustrates how sampling and digital equalization can expand at very high rates without eliminating the analog front end. |
| IEEE educational presentation, 2018 | Identified interconnect distance, channel loss, and power as primary scaling tradeoffs and highlighted PAM4 and ADC-based receivers as emerging architectures. | It frames the system-level tradeoffs rather than supplying a directly comparable implementation result. |
| IEEE report, 2025 | Reported 22.5 dB compensation at 28 GHz for an analog decision FFE. | This is evidence that analog equalization remains an active option; the stated figure alone does not establish performance under other channels, rates, or BER targets. |
Together, the examples argue against a simple “digital is newer, therefore better” rule. High-speed receivers can combine a substantial analog front end with deep digital equalization, while analog equalization can also deliver meaningful compensation. Compare results only when the channel, BER definition, rate, power boundary, and test conditions are sufficiently alike.
Quick Recap
How to choose an architecture for your link
- Characterize the channel. Obtain insertion-loss and return-loss data, calculate or measure loss at the signal’s Nyquist frequency, and identify crosstalk and reflection risks. Include the actual connectors, package, cable or trace, and fixtures in the model where possible.
- Set the timing and reliability limits. Define the total-jitter budget and its random and deterministic components, required eye opening, BER target, and any FEC threshold. Specify whether the BER limit applies before or after FEC.
- Place analog functions where the waveform demands them. Preserve analog output drive, termination, front-end gain, CTLE or peaking, and clock-generation capability wherever bandwidth, noise, or input conditioning is decisive.
- Choose digital functions for flexibility that pays for itself. Evaluate digital CDR control, FFE/DFE, calibration, lane deskew, monitoring, and firmware-selectable presets against their power, latency, area, and conversion overhead.
- Compare complete architectures against the same requirements. Evaluate reach, channel loss, BER, jitter tolerance, power per bit, area, latency, process sensitivity, supply-noise sensitivity, testability, and adaptation range. Do not compare only tap count or an isolated power number.
- Validate with models and measurements. Use channel models and measured S-parameters, eye diagrams, jitter decomposition, BER sweeps, differential probing, impedance and reflection checks, and corner testing. Include the intended operating conditions and the complete signal path.
Common design mistakes to avoid
- Treating “analog or digital” as a binary choice: Most practical high-speed designs allocate work to both domains.
- Assuming digital equalization rescues any input: The analog front end and ADC must still acquire a usable waveform.
- Choosing from a single power or jitter number: Check what circuitry is included, what channel was used, and the BER and measurement conditions.
- Ignoring the channel’s reflections and impedance: Attenuation is not the only signal-integrity concern. Xilinx’s multi-gigabit design guidance also calls out noise, reflections, jitter, dielectric loss, impedance matching, and transmitter-drive tuning.
- Using BER figures without their FEC context: A pre-FEC BER and a post-FEC BER describe different points in the link.
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