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Yes—but the evidence points to a specific later product, not to the 1 GHz demonstration itself. A contemporary report described a 1 GHz TMS320C64x fixed-point DSP running on a 130 nm engineering prototype; 90 nm production versions were then a forecast. TI’s later product bulletin identifies the TMS320TCI6482 as a 1 GHz C64+ DSP on 90 nm CMOS and connects TI’s manufacturing capabilities with volume-production support. That supports a product-specific account of 1 GHz, 90 nm DSP production, but does not establish present-day production or availability.
What did TI’s 1 GHz demonstration actually show?
The contemporary Test & Measurement World report described TI demonstrating a 1 GHz version of its TMS320C64x fixed-point DSP. The demonstration used a 130 nm engineering prototype—not the later 90 nm production part. The report said TI had introduced a 720 MHz version weeks earlier and expected 90 nm production versions to operate at nominal voltage and become available early the following year. That was a forecast at the time, not a statement about current availability. Read the archived Test & Measurement World report.
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How TI checked the prototype’s clock and computation
According to the report, TI applications engineer Todd Hiers fed a fractional clock to the device, used on-chip multiplication to reach a 1 GHz CPU rate, and measured a divide-by-four output at 250 MHz. A software check ran 512-point, 16-bit FFTs, which the report said took 3,206 cycles each. It also reported more than 156,000 such operations in half a second as evidence for a minimum 1 GHz clock. These are the report’s account of the demonstration, not independent test results.
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TI’s product bulletin identifies the TMS320TCI6482 as a C64+ DSP with a 1 GHz core and 90 nm CMOS. The bulletin also links TI’s manufacturing presence and 90 nm process capability to support for quality, supply, and volume production. Together, those details provide product-specific evidence for the title’s claim; they do not mean that every TI DSP built on 90 nm ran at 1 GHz. See TI’s TMS320TCI6482 product bulletin.
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Why was ramping to volume part of the story?
For a high-performance DSP, getting initial silicon to function was only one milestone. The contemporary report emphasized the engineering and test challenge of ramping production economically and quickly. TI advanced architecture manager and TI Fellow Ray Simar put it this way: “We have a big focus on ramp-to-volume. It’s not enough just to [successfully] tape out a design. Several years ago, we focused on ‘taping it out’ and getting the first ones to wiggle. Now, the key is how quickly we can ramp to volume.”
The report also said DSP testing could resemble system-on-chip testing more than standard microprocessor testing because configurations varied in memory size and peripheral mix. In that context, test strategy and production readiness mattered alongside peak clock speed.
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What the historical evidence does—and does not—establish
- Established: The reported 1 GHz demonstration used a 130 nm engineering prototype, while the article described 90 nm production versions as a future expectation. The contemporary report preserves that chronology.
- Established: TI’s TMS320TCI6482 bulletin specifies a 1 GHz C64+ core and 90 nm CMOS, and discusses manufacturing support for volume production. The product bulletin is specific to that device.
- Not established: These historical materials do not show the TCI6482’s current manufacturing status, current stock, or a production-volume unit count.
TI also published period roadmap material about C64x speeds and earlier 130 nm production-volume speeds. Such roadmap statements are not specifications for the TMS320TCI6482 and should not be substituted for its product bulletin. See TI’s period FAQ.
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