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A level 2 (L2) cache is the second tier of a processor’s cache hierarchy. It holds instructions or data that the processor is likely to need soon, so a request that misses the faster first-level (L1) cache can often be served from L2 instead of going all the way to main memory. Its size, speed and whether it is shared between cores all depend on the specific processor or system design, so there is no single L2 size or layout that applies to every chip.
Where L2 sits in the memory hierarchy
The term “level” describes position. Caches are arranged in a sequence from the one closest to the processor’s execution units to the one furthest away, and each step down trades some speed for more capacity. In a typical arrangement the order is:
- L1 cache: the smallest and closest tier, usually split into instruction and data caches in designs that document it that way.
- L2 cache: the next tier. It is larger than L1 and sits behind it.
- Further tiers: some designs add a third-level (L3) cache. Others go from L2 directly to main memory.
- Main memory: the system RAM, the last stop before the data has to come from storage.
The numbering therefore says nothing about whether L2 is physically private to one core or shared by several. That is a separate design decision, covered below.
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When a processor needs a piece of data or an instruction, the lookup proceeds in order through the levels. Each level either holds the item (a hit) or does not (a miss):
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- The processor checks L1. If the item is there, the request is finished.
- If L1 misses, the request moves to L2. If L2 holds the item, it is returned from L2 and main memory is not accessed.
- If L2 also misses, the request must be satisfied at a lower level. In Intel’s Pentium 4 microarchitecture, the L2 cache’s miss path leads to main memory through the system bus.
The value of L2 is that it catches many of the L1 misses before they reach that slower final step. Designs with an L3 cache insert that tier between L2 and main memory.
Documented examples of L2 designs
Vendor documentation describes L2 caches for specific products. These examples show how much the design can vary. They are not a description of every processor, and each one should be read with its architecture and date in mind.
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Intel Pentium 4 (2001 microarchitecture paper)
Intel’s paper “The Microarchitecture of the Pentium 4 Processor,” published in the Intel Technology Journal in 2001, describes the L2 cache as storing instruction bytes and data that cannot fit in the trace cache and the L1 data cache. When the L2 cache misses, the system bus accesses main memory. This is a clear example of L2 as an intermediate level. The paper does not give the L2 size or whether it was shared, so those details should not be assumed for that chip.
Intel XScale (third-generation microarchitecture manual, 2007)
Intel’s manual for the third-generation XScale microarchitecture describes its L2 as optional and as the next level of the memory hierarchy below the L1 instruction and data caches. The manual lists 256 KB and 512 KB as configuration options for that family. These values apply to that embedded processor family and do not describe L2 caches in general.
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AMD Versal ACAP CPM CCIX (architecture manual AM016, revision 1.1, 24 November 2020)
AMD’s architecture manual for the Versal ACAP CPM CCIX block includes a “Level 2 Cache” chapter. It describes an integrated shared L2 cache intended to reduce latency and bandwidth demands for accesses between accelerators and memory. For this implementation, the manual specifies a 1 MB cache that is physically addressable and physically tagged, with 64-byte cache lines. These figures belong to that product and revision and should not be applied to other AMD parts.
Intel 12th Gen Core hybrid architecture (developer guide)
Intel’s game developer guide for the 12th Gen Intel Core hybrid architecture states that the L2 cache for the logical E-core processor is shared in banks of four logical processors. This is a useful reminder that L2 sharing depends on how the processor is organized. A hybrid design does not give every core its own L2, and it does not mean all L2 caches are shared across the whole chip.
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Comparing the examples
| Example | Source and date | L2 position | Documented L2 size | Sharing |
|---|---|---|---|---|
| Intel Pentium 4 | Intel Technology Journal, 2001 | Behind the trace cache and L1 data cache; misses go to main memory | Not stated in the source | Not stated in the source |
| Intel third-generation XScale | Intel manual, 2007 | Optional next level below the L1 instruction and data caches | 256 KB or 512 KB options | Not stated in the source |
| AMD Versal ACAP CPM CCIX | AMD manual AM016 rev. 1.1, 24 Nov 2020 | Integrated L2 for accelerator-to-memory accesses | 1 MB, physically addressable and tagged | Integrated shared L2 |
| Intel 12th Gen Core hybrid (E-core) | Intel developer guide for 12th Gen Core hybrid architecture | L2 for the logical E-core processor | Not stated in the source | Shared in banks of four logical processors |
The table shows why a single definition has to stay general. Each row is correct only for its own product, and the blanks are gaps in the cited documents rather than evidence that those caches lack a size or sharing arrangement.
Why L2 size and sharing vary
Designers choose L2 capacity and sharing according to the workload and the chip’s layout. A larger L2 can hold more of the working set but takes more silicon area and can be slower to access. A shared L2 lets cores use the same pool of cached data, while a private L2 keeps each core’s data separate and avoids contention between them. Because these choices differ by product, the only reliable way to know the L2 configuration of a given processor is to check its own technical documentation.
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How to find the L2 size on your own computer
- Windows: open Task Manager, select the Performance tab, then select CPU. The panel lists L1, L2 and L3 cache sizes for the processor.
- Linux: run
lscpuin a terminal and look for the “L2 cache” line. The output may include a count such as “(4 instances)”, which means the figure is the total across that many cache instances, not the size of a single one.
Check whether a reported value is per core or total before comparing it with a spec sheet. On hybrid processors, the figures can differ between core types.
What L2 size does not tell you
A larger L2 is not automatically faster in real use, and the cache level alone does not establish a processor’s speed. The documents above do not provide universal latency values for L2 caches, and no benchmark in them compares L2 designs across all processors. For a real comparison, use the exact model’s documented L2 capacity and sharing, then look at independent performance tests for the workloads you care about.
The safest way to describe L2 is as a position in the hierarchy: the tier that handles requests that miss L1 and stands between the processor and main memory, with its size and layout set by each processor’s design.
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