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Yes—as a long-range technology-generation target, 1nm semiconductor technology is plausible. No commercial 1nm process is established by the announcements and research described here. In this context, “1nm” is a node label, not a claim that every transistor feature measures one nanometer. The path imec describes depends on coordinated advances in transistor design, materials, contacts, wiring and patterning—not simply shrinking every dimension.
What does “1nm” mean?
A semiconductor node name identifies a technology generation; it does not, by itself, specify the size of a particular transistor feature. To understand a physical dimension, look for the measurement being reported. Gate length describes the channel dimension controlled by the gate. Gate pitch describes the repeated spacing between gates in a layout. Metal pitch describes spacing in the wiring layers. These are distinct measurements, so a “1nm node” claim would not establish that gate length, gate pitch or metal pitch is 1nm.
The distinction is visible in the reported figures. TSMC’s 2019 explainer gave about 20nm as a typical transistor gate length at that time—a historical example, not a universal current specification. Intel reported CFET research at a 60nm gate pitch in work presented at IEDM 2023, and later reported monolithic CFET inverter research at a 45nm gate pitch at the 2026 VLSI Symposium. Neither measurement is a 1nm node specification.
What could a route to a 1nm generation involve?
Imec’s proposed scaling path changes both transistor architectures and the surrounding manufacturing stack. The roadmap moves from FinFETs toward gate-all-around (GAA) nanosheet FETs, then considers forksheet devices and complementary FETs (CFETs), which vertically stack n-type and p-type transistors. Imec describes this collection of options as a “possible path towards the 1nm technology node”—a roadmap proposal, not a statement that such a process is already ready for production.
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Transistor architectures
GAA nanosheets are the next architectural step identified in the roadmap after mainstream FinFETs. Imec’s Naoto Horiguchi, then director of CMOS device technology, said foundries and integrated device manufacturers had announced transitions to GAA nanosheet architectures for their 3nm or 2nm logic generations. He described forksheets as a way to extend the nanosheet generation, with CFETs anticipated afterward on the scaling roadmap. These are proposed stages in a technology path; the sequence does not guarantee that every manufacturer will adopt every architecture.
CFETs stack complementary transistor types vertically rather than placing them side by side. That approach is being investigated as a way to continue scaling beyond GAA devices, but the reported gate-pitch results are research demonstrations, not evidence of a production node.
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Channels, contacts and wiring
Imec identifies 2D channel materials and atomic channels as research directions for the 1nm generation and beyond. Intel has also reported research on 2D transition-metal dichalcogenide transistors aimed at physical gate lengths below 10nm. A research target of that kind is not a commercial manufacturing commitment.
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What recent company announcements establish—and what they don’t
| Announcement or result | What it says | What it does not establish |
|---|---|---|
| Intel, IEDM 2023 research | Vertically stacked CFET research with gate pitch down to 60nm; separate 2D transistor research aimed at physical gate lengths below 10nm. | A commercial 1nm process or a 1nm physical gate dimension. |
| Intel, 2026 VLSI Symposium announcement | Monolithic CFET inverter research at a 45nm gate pitch, presented as a long-term path beyond GAA transistors. | A production-ready process or a 1nm node measurement. |
| TSMC, April 2026 A13 announcement | A13 uses TSMC’s nanosheet transistor technology, is scheduled for production in 2029, and is described as providing 6% area savings from A14. | A declaration that A13 is a 1nm node, or a confirmed production date for a 1nm generation. |
The A13 schedule and area figure belong specifically to TSMC’s April 2026 announcement. They should not be treated as evidence about when a different, commercial 1nm generation will arrive.
Why a roadmap is not a production forecast
A candidate device architecture must be integrated with contacts, interconnects, lithography and other process steps. It also has to meet requirements for reliability, yield and cost. A successful laboratory demonstration or roadmap proposal can show that a direction is worth pursuing without showing that the full manufacturing process is ready, economical or scheduled for high-volume production.
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There is no firm commercial 1nm production date established by the sources cited here. Imec’s roadmap sets out a possible path, while the Intel results are explicitly research and TSMC’s 2026 announcement concerns A13. None of those facts supplies a reliable date for high-volume production of a 1nm technology generation.
How to evaluate future “1nm” claims
- Check what “1nm” labels. Is it a process generation, or does the source give a physical dimension?
- Identify the measurement. Gate length, gate pitch and metal pitch describe different things; do not substitute one for another.
- Look for the status. Is the item a research demonstration, a roadmap option, a production announcement or evidence of high-volume manufacturing?
- Read the scope of any number. Note who reported it, when, and whether it describes a research result, a specific process generation or a scheduled production milestone.
- Look beyond the transistor. A scaling proposal also needs a workable plan for contacts, wiring, materials, patterning and process integration.
TSMC’s 2019 corporate explainer characterizes Moore’s Law as a guideline based on historical observation and future prediction, rather than a literal law. That perspective fits the question: technology roadmaps can describe plausible scaling directions, but they do not make a particular generation inevitable.
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