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Yes—Markus Nentwig’s Hackster.io project reports a real-time 1920×1080, 60 Hz Julia/Mandelbrot-style renderer on a Digilent Cmod A7-35T powered from USB, with an approximately 2 W bus-power budget. Those figures are the project author’s reported design results and targets, not independent measurements. The implementation uses direct VGA-style wiring rather than HDMI.
What the project actually demonstrates
The build is a specific FPGA implementation, not proof that every small FPGA can render 1080p fractals at 60 Hz. Nentwig reports a 148.5 MHz VGA pixel clock, a 200 MHz fractal-calculation engine and a 100 MHz J1B soft-core CPU. The project was published January 18, 2020.
| Item | Project-reported value | Qualification |
|---|---|---|
| Active video format | 1920×1080 progressive | Author’s stated design result |
| Frame rate | 60 Hz | Author’s stated design result |
| Pixel clock | 148.5 MHz | Reported VGA timing; also the standard figure commonly used for 1080p60 timing |
| Fractal engine clock | 200 MHz | Author-reported clock |
| J1B CPU clock | 100 MHz | Author-reported clock |
| USB power | Approximately 2 W | Stated bus-power budget, not an independently documented measurement |
The author summarizes the relationship this way: “The 200 MHz clock rate of the fractal generator is less than two times the VGA pixel rate.”
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FPGA board
The design uses one Digilent Cmod A7-35T module. Nentwig says the design is too large for the Cmod A7-15T variant, so the device size is part of the implementation’s feasibility rather than an incidental board choice.
#1 Best Overall
- The only difference between the Cmod A7-15T and Cmod A7-35T are the capabilities of the FPGA found on the board.
- Small breadboard-friendly 48-pin DIP form factor board perfect for digital logic circuits and Microblaze embedded soft-core processor designs
- On board user interfaces include 2 LEDs, 1 RGB LED, and 2 push buttons
- Expansion opportunities with a 48-pin DIP connector and one Pmod connector with 8 Digital I/O
- Free software with Vivado Design Suite (WebPACK Edition)
Wiring and software
- Generic jumper wires are listed hardware.
- Vivado Design Suite is the documented toolchain.
- The rebuild instructions specify Vivado 2019.2.
- The demo can be run by uploading the project’s prebuilt bitstream instead of rebuilding it.
These are the project’s documented requirements; they do not establish current board stock or present-day software support.
How the fractal pipeline keeps up
Parallel calculation engines
The design describes 30 parallel calculation engines. Each engine has 12 pipeline levels and uses three multipliers, for 90 multipliers across the engine array. Pipelining lets new work enter while earlier points continue through the arithmetic stages.
Rank #2
- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
Dynamic dispatch for uneven workloads
Escape-time fractals do not require the same number of iterations for every pixel. Points that escape quickly finish sooner than points near a set boundary. A coordinate generator scans the image and dispatches each point to whichever engine can accept it, rather than assigning every pixel a fixed, worst-case schedule. That variable-work approach reduces idle time caused by waiting for a long-running pixel.
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Flow control and buffering
Results cannot be allowed to run indefinitely ahead of the display position. The project uses valid/ready handshaking, segmented FIFOs and flow control to limit result-buffer growth and avoid an unnecessarily long combinational ready path. In practical terms, the arithmetic pipeline and the video scanout are decoupled, but only within bounded storage and scheduling rules.
Rank #3
- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
Clock domains and 1080p timing
The reported design separates three timing domains:
- 200 MHz: fractal calculation engine.
- 148.5 MHz: VGA pixel timing for 1920×1080 at 60 Hz.
- 100 MHz: J1B soft-core CPU.
A separate FPGA HDMI timing reference also lists 148.5 MHz for 1920×1080 progressive at 60 Hz. That corroborates the timing figure, but it does not document this project’s circuitry or guarantee that another FPGA can generate the same output. I/O capability, clocking resources and the chosen signaling method remain board-specific.
Rank #4
- Arty S7 comes in two FPGA variants: Arty S7-25 features Xilinx XC7S25-CSGA324. Arty S7-50 features the larger Xilinx XC7S50-CSGA324.
- Internal clock speeds exceeding 450MHz
- On-chip analog-to-digital converter (XADC)
- Programmable over JTAG and Quad-SPI Flash
- Powered from USB or any 7V-15V source
Output is direct VGA-style wiring, not HDMI
The project connects red, green, blue, HSYNC, VSYNC and a common ground from the board socket to a monitor cable. The author explicitly warns that 3.3 V is outside the analog VGA signal specification. Therefore, this wiring should be understood as the author’s direct experimental approach, not general standards-compliant VGA advice.
- Use a compatible VGA monitor and cable path, not an HDMI cable by substitution.
- Do not describe the output as HDMI or assume TMDS serialization is present.
- Check the electrical interface before connecting other equipment; a 3.3 V FPGA output is not automatically a properly scaled analog VGA signal.
Why other FPGA fractal projects may not reach the same result
Implementation outcomes depend on more than the fractal algorithm. A separate Artix-7 Mandelbrot project reports 20 fractal slices quadruple-pumped at 300 MHz but only about a 65 MHz pixel clock. Its author says the selected board could not reliably support 1080p because the required serializer speed exceeded the device’s limits, and also describes brownout when logic load increased.
Best Value
- Digilent Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users
Those are board- and design-specific observations, not evidence that the Cmod A7-35T build has the same faults. They illustrate the checks required in any reproduction:
- Available LUTs, DSP/multiplier blocks, RAM and clocking resources.
- Output-interface limits, especially if converting from direct VGA to HDMI/TMDS.
- Power integrity under peak logic activity.
- Arithmetic precision and the maximum iteration depth selected for the image.
- Buffer capacity and back-pressure behavior when work completion is highly uneven.
What “real-time on USB power” means here
In this project, “USB power” refers to the board’s approximately 2 W bus-power budget as stated by the author. No named independent power measurement is documented, so the figure should not be treated as a lab-verified consumption result or as a universal USB-power guarantee. The 60 Hz claim likewise belongs to this implementation’s report.
Practical reproduction checklist
- Use the Digilent Cmod A7-35T rather than the smaller 15-size variant identified as insufficient for this design.
- Install the project’s specified Vivado 2019.2 environment if following its documented rebuild flow.
- Choose either the supplied bitstream demonstration path or a source rebuild.
- Recreate the documented RGB, HSYNC, VSYNC and ground connections to a VGA monitor cable.
- Verify electrical levels and monitor compatibility before applying the direct 3.3 V wiring.
- Confirm that the generated clocks, timing constraints and resource utilization close on the target device.
- Measure USB current with suitable equipment if power consumption matters; the project’s approximately 2 W value is a budget claim, not a published independent measurement.
Bottom line for engineers
The Cmod A7-35T project is a credible example of using many pipelined arithmetic engines and dynamic scheduling to target 1920×1080 at 60 Hz within a small USB-powered FPGA system. Its defining details are the 30-engine, 12-stage pipeline, 90-multiplier arithmetic array, separate 200/148.5/100 MHz clock domains and direct VGA-style output. Treat the headline frame rate and power as Markus Nentwig’s reported results, and treat the electrical interface, serializer needs and power behavior as issues that must be revalidated on any different board or output design.
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