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For an ADC used in communications, bit depth alone does not predict how cleanly it handles real signals. This part of the series explains how to assess spurious-free dynamic range (SFDR), intermodulation distortion (IMD), noise-power ratio (NPR), and the timing errors caused by sampling-clock jitter.
What this part of the series covers
“Basics of ADCs and DACs, part 4” was written by Walt Kester and James Bryant of Analog Devices and published on August 9, 2007. It focuses on ADC dynamic performance: unwanted spectral products, behavior under multiple signals, and sampling-clock timing. The series is based on chapter 2 of Walt Kester’s Mixed-Signal and DSP Design Techniques. Part 3 covers ADC distortion and noise; part 5 turns to DAC performance, including glitches and rolloff.
What SFDR means for an ADC
Spurious-free dynamic range is the ratio of the rms amplitude of the wanted signal to the rms amplitude of the largest spurious spectral component. It is measured over the first Nyquist zone, from dc to half the sampling frequency (fs/2). SFDR is expressed in dBc when referenced to the signal, or in dBFS when referenced to full scale.
Analog Devices’ article calls SFDR probably the most significant ADC specification for communications applications. A large unwanted spur can interfere with a weak signal even when the converter’s overall noise performance looks good. Resolution alone is not a reliable SFDR proxy: adding bits may improve SNR, but SFDR may improve or remain limited by distortion.
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AD9042 example in the 2007 article
The article cites the Analog Devices AD9042, a 12-bit, 41-MSPS converter. With a 19.5 MHz input, it achieves at least 80 dBc SFDR across the first Nyquist zone, dc to 20 MHz. The same example gives 65 dBc typical SNR and 74 dB theoretical SNR. These are figures for that named converter and test context, not general expectations for 12-bit ADCs.
How a two-tone IMD test works
A two-tone test applies two sine waves at nearby frequencies and observes distortion products created by their interaction in the converter. Each tone should be set slightly more than 6 dB below full scale so that their combined waveform does not clip when the tones add in phase.
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Third-order intermodulation products occur at 2f2−f1 and 2f1−f2. Because these products lie close to the wanted tones, filtering them out is difficult; their size is useful for judging converter linearity in applications carrying multiple channels.
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What NPR reveals about a heavily loaded ADC
Noise-power ratio testing models a band of many signals by passing noise through a notch filter, then measuring how much noise appears in the notch after conversion. At low loading, the in-notch level is mainly quantization noise. As the total input loading rises, clipping and intermodulation distortion raise the apparent noise floor in the notch.
In the AD9042 example, the article reports 60 dB measured NPR versus 62.7 dB theoretical NPR. Those figures describe that example, not a universal NPR for ADCs or a result transferable to other input conditions.
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How aperture jitter limits SNR
Aperture jitter is uncertainty in the instant the ADC takes a sample. If the input voltage is changing quickly at that instant, even a small timing error produces a larger voltage error than it would on a slowly changing signal. As a result, jitter-driven SNR degradation becomes more severe as input frequency rises.
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The clock path matters, not just the oscillator. Sampling-clock phase noise and jitter can accrue through the oscillator, transmission path, and converter clock input; the ADC’s integral sample-and-hold can also contribute aperture jitter. Keep the clocking chain low-noise, especially when digitizing high-frequency signals.
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The article notes that an external high-performance sample-and-hold can sometimes improve high-frequency effective number of bits (ENOB) by presenting a near-dc signal to the ADC. This is an application-dependent design option, not a guarantee of improvement.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What aperture delay means
Aperture delay is the fixed timing offset between the sampling clock reference and the ADC’s effective sampling instant. A fixed delay by itself does not create a conversion error; it shifts when the input is sampled. Differences in delay between converters matter when channels must sample together, such as in simultaneous-sampling or I/Q systems, because mismatched timing can undermine alignment.
How to compare ADCs for these behaviors
For a communications or multichannel design, compare specifications and measurements under conditions close to the intended use rather than relying on bit count alone.
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- SNR, SNDR, and ENOB at the target frequency: noise and distortion measurements vary with input frequency and test setup.
- Two-tone and multitone IMD: assess whether nearby unwanted products could interfere with weaker channels.
- NPR or overload behavior: useful where a dense set of channels or high aggregate signal level is expected.
- Aperture-jitter sensitivity and clock phase noise: especially important at high input frequencies.
- Aperture-delay matching: relevant when multiple channels must track or maintain I/Q timing.
The article also notes a 33 dB process gain for a 4096-point FFT. Treat FFT process gain as part of the measurement context: it affects how low a spectral component can be distinguished in an FFT-based analysis, rather than changing the ADC’s intrinsic SFDR.
Further reading
For a deeper treatment, see Walt Kester’s Mixed-Signal and DSP Design Techniques, the reference text on which this Analog Devices series is based. The associated Analog Devices article is available at Basics of ADCs and DACs, part 4.
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