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ASML’s nearly $2 billion 2016 program with Carl Zeiss SMT was designed to develop High-NA EUV lithography, the next generation of chip-patterning technology. A decade later, High-NA has reached production use at Intel, while TSMC has set a later target for adopting it at advanced nodes.
What ASML’s nearly $2 billion funded
In November 2016, EE Times reported that ASML planned a package of investment and development spending totaling nearly $2 billion. The reported components were:
- About $1.1 billion in cash for a 24.9% stake in a Carl Zeiss subsidiary.
- About $244 million as a one-time contribution to a joint research and development project.
- About $600 million over six years for capital equipment and other needs.
These are the amounts and terms reported in 2016; they are rounded figures, not a current valuation of ASML’s interest. ASML’s investor materials describe its 24.9% indirect interest in Carl Zeiss SMT as supporting further EUV development and aligning the companies’ long-term roadmaps, including High-NA.
Why ASML invested in Zeiss SMT
ASML builds EUV lithography scanners, but their ability to pattern ever-smaller features depends on the optical systems that direct and focus light. Carl Zeiss SMT supplies the precision optics central to that work. An ownership stake and joint development funding gave the companies a way to coordinate on difficult, long-lead optical technology rather than treating the scanner and its optics as separate projects.
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The investment was also a strategic commitment to a technically risky next step. In 2016, VLSI Research president Risto Puhakka told EE Times that ASML had not previously taken a direct investment stake with a supply-chain partner and that the size of the investment signaled confidence in the new systems as well as the risks involved. The stake was in a Zeiss subsidiary; it did not make ASML the owner of Zeiss as a whole.
What High-NA EUV is—and how it differs from established EUV
EUV lithography uses light with a wavelength of 13.5 nanometers and mirrors to project a photomask’s pattern onto a silicon wafer. “NA” means numerical aperture: a measure of how much light an optical system can collect and focus. High-NA systems use a larger numerical aperture, collecting light over a wider angular range to resolve finer features.
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| Comparison | Established EUV | High-NA EUV |
|---|---|---|
| Numerical aperture | 0.33, according to ZEISS’s current technical overview | 0.55, according to ZEISS’s current technical overview |
| Resolution | Not stated in ZEISS’s cited technical overview | Below 10 nanometers, according to ZEISS |
| Optical design | Not stated in the cited overview | Larger illumination and projection optics are needed to handle the wider angular range |
| Mask format and rollout | Not stated in the cited overview | Intel reports current production options using 6-inch masks; ASML and TSMC are working toward a future 12-inch-mask ecosystem |
ZEISS says High-NA can put around three times more structures in the same area than established EUV. That is a lithography capability, not a promise that every chip will become three times denser: designs, materials, process rules, and manufacturing choices affect what a chipmaker can use in practice.
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Why High-NA optics are so demanding
Collecting and focusing light at NA 0.55 requires much larger optical assemblies than those used for established EUV. ZEISS’s current technical overview describes a High-NA projection-optics system with more than 40,000 parts and a weight of about 12 tons, plus an illumination system weighing about six tons. ZEISS says about 2,000 of its SMT employees work on High-NA EUV.
Making those optics is itself a major engineering undertaking. ZEISS says its mirrors are manufactured to atomic precision and take about a year to produce. They are measured repeatedly using a vacuum-chamber system measuring five by ten meters and weighing roughly 150 tons. These manufacturing and metrology demands help explain why optics and the supplier ecosystem were central to ASML’s long-term investment, rather than incidental components of a scanner program.
When High-NA EUV reached production—and what comes next
The 2016 EE Times report said systems with a numerical aperture greater than 0.5 would not be ready for volume production until about 2024. The subsequent rollout has been staged: installation, qualification, research and development, and customer production are different milestones, not one universal launch date.
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Intel: production use reported in 2026
In a September 8, 2026 release, Intel and ASML said High-NA EUV was being used in high-volume manufacturing at Intel Foundry. They reported that more than one million wafers had been processed with High-NA across certification, testing, R&D, and volume production combined. That figure does not mean more than one million wafers were made in volume production alone. The release identified selected layers of Intel Core Ultra Series 3, also known as Panther Lake, as using High-NA.
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TSMC: intended adoption from 2030
In a September 8, 2026 announcement, TSMC and ASML said TSMC intends to use High-NA EUV in high-volume manufacturing for advanced nodes starting in 2030. Their related large-format photomask initiative targets a 12-inch mask pilot line by 2031 and 12-inch High-NA lithography systems entering advanced-node production by 2033. These are stated targets, not evidence that those milestones have already occurred.
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What High-NA could mean for future chips
Higher resolution can help chipmakers pattern smaller features. For leading-edge logic and memory, High-NA may also reduce the number of patterning steps needed for some layers. Neither outcome is automatic: manufacturers have to qualify the scanner and integrate it into a working production process, alongside masks, materials, automation, electronic-design tools, and fab procedures.
Mask format is one example of that ecosystem work. Intel has reported production options using current 6-inch masks. ASML and TSMC are coordinating a longer-term move toward 12-inch masks, which ASML says could improve scanner productivity. The transition has its own development and production targets, so the optics alone do not determine when every customer or process node will adopt High-NA.
For AI chips specifically, High-NA is a manufacturing tool—not a chip design or a guarantee of a particular performance gain. It may help enable future generations of smaller, denser logic or memory, but whether an AI processor uses High-NA depends on its manufacturer’s process choices and production schedule. The 2026 Intel announcement provides a concrete example of selected product layers using the technology; it does not establish that all AI chips, or all layers in a given chip, use High-NA.
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