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About 55% was an analyst’s estimate of TSMC’s early-ramp 3nm yields for Apple’s A17 and M3 processors in 2023—not an official, audited yield figure disclosed by TSMC. The analyst called it healthy for that stage of development and expected improvement as production matured.

What the 55% figure means—and what it does not

Brett Simpson, a senior analyst at Arete Research, estimated that yields for TSMC’s N3 process used for Apple’s A17 and M3 processors were around 55% during the early ramp, according to EE Times in 2023. In semiconductor manufacturing, yield broadly refers to the share of manufactured dies that meet the requirements to be usable. The report does not establish that every N3 customer, product, or production batch had the same yield.

The estimate was not a TSMC product-yield disclosure. TSMC chief executive C.C. Wei separately said N3 had reached high-volume production with “good yield,” while customer demand exceeded the company’s ability to supply. Those comments describe the company’s assessment of the process and its supply situation; they do not confirm Simpson’s 55% estimate.

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What the analyst reported about the A17 and M3

Arete Research’s reported figures describe estimates and expectations from the early N3 ramp, rather than final production results:

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Measure Reported figure Qualification
N3 yield for Apple A17 and M3 processors About 55% Analyst Brett Simpson’s early-ramp estimate, reported by EE Times in 2023; not an official TSMC yield disclosure.
Expected yield improvement Around 5 or more percentage points per quarter Simpson’s expectation at the time, not a subsequently verified quarterly result.
Yield level associated with initial-ramp pricing Roughly 70% Reported as the level toward which yields would move during the first three to four quarters of the ramp; not a claim that all products reached it on a fixed schedule.
A17 die size Estimated 100–110 mm² Arete Research estimate reported by EE Times in 2023.
Mask layers 82 Arete Research figure reported by EE Times in 2023.
Estimated chips per wafer About 620 A17 chips; about 450 M3 chips Arete Research estimates reported by EE Times in 2023; the figures are not a guaranteed count of usable chips from every wafer.

Wafer-level chip counts and yield are different measures. The reported counts estimate how many dies can be laid out on a wafer; yield concerns how many manufactured dies are usable. A chip count alone therefore does not establish how many finished, usable processors a wafer produced.

Which Apple products were connected to the N3 ramp?

A17 Bionic: iPhone 15 Pro models

The A17 was expected for Apple’s iPhone 15 Pro models. That made the early N3 ramp directly relevant to a consumer product, but the reported yield estimate does not say how many iPhone units Apple shipped or whether a particular device experienced a supply shortage.

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M3: Macs

The M3 processors were being developed for Macs. Simpson’s estimate covered the A17 and M3 together; it should not be read as a separately disclosed yield for every M3 chip or Mac model.

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Could a 55% yield make Apple’s M3 more expensive?

Lower yield can mean fewer usable dies from a given amount of wafer production, which can raise manufacturing cost per usable chip if other factors stay the same. But the reported estimate alone cannot establish Apple’s actual M3 cost, retail price, or profit margin.

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EE Times reported that Apple was paying for known-good dies rather than using standard whole-wafer pricing during the first three to four quarters of the ramp, as yields moved toward roughly 70%. Under a known-good-die arrangement, payment is tied to dies that meet the agreed usability criteria rather than simply to the wafer. That pricing basis can change how ramp risk is shared, but it does not reveal the price Apple paid per chip or prove that any cost change was passed on to customers.

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What TSMC said, and what later reporting does not prove

Wei said TSMC’s 3nm technology had reached high-volume production with good yield. He also said demand for N3 exceeded the company’s ability to supply it and that TSMC expected the process to be fully utilized in 2023, supported by high-performance computing and smartphone applications. A demand-driven supply constraint is distinct from a low-yield claim: the CEO’s remarks do not identify yield as the reason supply could not meet demand.

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TSMC’s 2025 annual report continued to place 3nm among the process nodes driving flagship smartphone SoCs. That later description indicates the node remained commercially important; it does not independently confirm the historical 55% estimate for the A17 and M3 ramp.

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