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AMD’s Versal AI Edge Series Gen 2 adds AIE-ML v2 tiles, new MX6 and MX9 data types, and a redesigned processing system. AMD says the AI engines can provide about twice the compute per tile and projects up to 3× higher TOPS per watt than first-generation Versal AI Edge devices—but the latter is a company projection, not an independent benchmark. The family spans devices with 24 to 144 AI-engine tiles, and its listed dense INT8 performance ranges from 31 to 184 TOPS.
What changed in Versal AI Edge Gen 2?
AMD announced Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 on April 9, 2024. AI Edge Gen 2 is an adaptive system-on-chip that combines programmable logic, AIE-ML v2 AI Engine tiles, and integrated Arm CPUs. The intended division of work is to use programmable logic for real-time preprocessing, the AI engines for inference, and the CPUs for postprocessing and system tasks.
The AI Edge Gen 2 product specifications identify AIE-ML v2 tiles, support for MX6 and MX9 data types, and device configurations ranging from 24 to 144 tiles. AMD says each tile is designed to deliver about twice the compute of a previous-generation tile. These are product claims, not a promise that every application will run twice as fast: realized performance depends on the model, data type, implementation, memory access, and system design.
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AMD’s figures describe different measures and should not be treated as interchangeable benchmark results.
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| Measure | AMD’s stated figure | How to interpret it |
|---|---|---|
| Compute per AI Engine tile | About 2× versus the previous generation | AMD’s product-page design claim; application speed depends on how well the workload maps to the device. |
| AI performance per watt | Up to 3× versus first-generation Versal AI Edge | A 2024 AMD projection based on internal performance and power estimates, comparing MX6 with first-generation INT8 conditions. It is not a universal measured result. |
| Scalar processing-system compute | Up to 10× versus first-generation Versal AI Edge and Prime devices | An AMD launch comparison for the new processing system, not a claim that every CPU-bound workload will be 10× faster. |
| Processing-system compute | Up to 200k DMIPs on supported configurations | A maximum listed by AMD for supported configurations; it does not apply to every part. |
AMD’s listed dense performance varies by device and data type:
| Listed device(s) | Dense INT8 performance | Dense MX6 performance |
|---|---|---|
| 2VE3304 / 2VE3358 | 31 TOPS | 61 TOPS |
| Range across listed AI Edge Gen 2 devices | 31–184 TOPS | 61–369 TOPS |
| 2VE3804 / 2VE3858 | 184 TOPS | 369 TOPS |
These are AMD product specifications for dense operations, not independent measurements of application throughput. The MX6 figures use a different data type from INT8, so compare values only when the workload can use the corresponding format and its accuracy and implementation requirements are acceptable.
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How does AI Edge Gen 2 differ from the other Versal families?
AMD’s series comparison distinguishes the product lines by their AI Engine generation and type:
| Series | AI Engine identified by AMD |
|---|---|
| Versal AI Edge Series Gen 2 | AIE-ML v2 |
| Original Versal AI Edge | AIE |
| Original Versal AI Core | AIE-ML |
| Versal Prime Series Gen 2 | AIE |
The names alone do not determine which family is the better fit. Compare the exact device’s AI capacity and data types with the workload, then assess scalar processing, programmable-logic needs, I/O and memory bandwidth, latency, safety and security requirements, and software support.
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Where can the architecture be useful?
AMD describes AI Engines as scalable two-dimensional arrays of processor tiles for compute-intensive DSP and machine-learning workloads. Its examples include 5G beamforming, automotive perception and advanced driver-assistance systems, industrial and factory systems, medical imaging, and aerospace and defense.
The integrated mix of programmable logic, AI engines, and Arm CPUs is most relevant when a design needs to combine real-time sensor conditioning, inference, and control on one device. A discrete GPU, NPU, or FPGA may be a better fit when the workload, latency and power constraints, or software ecosystem favor separating those tasks. The performance figures above do not establish that one architecture will outperform another for a particular application.
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Can developers use Vitis and Vivado?
AMD’s June 5, 2025 availability update said Vitis and Vivado 2025.1 moved the product lines to general access. AMD said customers could review product documentation and evaluate the devices with the Vivado Design Suite and Vitis Unified Software Platform. That announcement marked a tooling-access milestone; it does not mean every device and speed grade is supported in every release.
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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsProduction support is version- and part-specific. AMD’s DS1021 production-status document, released July 1, 2026, lists 2VE3804 and 2VE3858 entries referencing Vivado 2025.2 v2.00 or Vivado 2026.1 v2.02. Some 2VE3504 and 2VE3558 combinations require Vivado 2026.1 v2.01. Check the DS1021 entry for the exact part and speed grade before selecting a tool release or committing a design; a family-level statement of availability is not enough to confirm production support for a specific configuration.
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What to check before choosing a device
- Map the workload to its data type. Confirm whether the model can use INT8, MX6, or another supported format, and evaluate accuracy as well as throughput.
- Size the full pipeline. Account for preprocessing, inference, postprocessing, memory movement, and I/O rather than selecting a part from its TOPS figure alone.
- Check system constraints. Compare latency, power, programmable-logic flexibility, scalar CPU capacity, and required safety or security capabilities against the application.
- Verify software and production status. Match the specific device and speed grade to the applicable Vivado version and status in AMD’s production documentation.
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