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Agile methods can work for chip design when teams replace a single high-stakes final tapeout with a sequence of smaller, useful prototypes. In this 2015 article, UC Berkeley professors David Patterson and Borivoje Nikolić recommend making designs scalable, using prototypes for verification and validation, improving hardware-code reuse, and preserving software compatibility. Their figures describe the period and examples discussed in that article—not current foundry prices or universal project costs.
What does “agile” mean for hardware design?
In software, teams can often build and test changes quickly. Chip fabrication is slower and more expensive, so a hardware team cannot simply treat every change like a software release. Patterson and Nikolić’s approach is to build a sequence of small, working but incomplete prototypes, learning from each iteration rather than waiting for one large, final “Big Tapeout.”
The goal is not to make silicon iteration instantaneous. It is to reduce the cost and risk of finding problems late, by getting useful implementations into a feedback loop earlier. A prototype can test selected functionality, integration, performance, or energy behavior without representing the finished product.
How much did the 28 nm prototype run cost?
An EE Times/Design-Reuse table cited in the 2015 article reports a 28 nm prototype run totaling about $30,000. It lists 80–100 dies and an average cost of $300–$375 per untested die; the smallest die in the table measured 1.57 × 1.57 mm. These are reported case-study figures from 2015, not a current quote or a general price for manufacturing prototypes.
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| Reported 2015 28 nm prototype-run measure | Value |
|---|---|
| Total run cost | About $30,000, according to the EE Times/Design-Reuse table cited in the 2015 article |
| Dies produced | 80–100, according to the EE Times/Design-Reuse table cited in the 2015 article |
| Average cost per untested die | $300–$375, according to the EE Times/Design-Reuse table cited in the 2015 article |
| Smallest die | 1.57 × 1.57 mm, according to the EE Times/Design-Reuse table cited in the 2015 article |
The example supports a method, not a price forecast: make a small configuration worth building and testing, then increase its scale when the design’s requirements warrant it. A design that is useful at a smaller die area gives a team a way to learn without making every early prototype carry the area—and manufacturing cost—of the eventual full system.
Why use prototypes for verification and validation?
The article separates two questions. Verification asks whether the team built the design right: does it implement the intended specification? Validation asks whether it built the right thing: does the design meet the needs of the intended use? Prototypes can contribute to both, but they answer different questions.
Simulation remains valuable for checking behavior, but the authors argue that running a design on FPGA or prototype silicon provides execution feedback much faster than simulation. Their 2015 article gives FPGA prototypes a 10–20× slowdown relative to chip prototypes. That is still slower than a finished chip, but the point is that an FPGA can exercise software and system behavior at a pace that helps expose performance, energy, and integration concerns sooner than simulator-only feedback. The figure is the article’s reported comparison, not a universal ratio for every design or toolchain.
An agile verification and validation loop uses each implementation to reduce uncertainty. Teams can test the parts that are ready, learn which assumptions fail, and make changes before committing to a larger implementation. This does not remove the need for final verification or guarantee that a prototype will reveal every defect; it changes when the team can gather useful evidence.
How can teams shorten the iteration cycle?
Part I of the series provides the process context. It describes multi-project wafers, in which multiple designs share a reticle so mask costs can be spread across projects. It contrasts an approximately four-month fabrication-and-evaluation cycle with a one-to-three-year waterfall cycle, and describes “tape-ins”: designs prepared to tapeout quality but held for the next available cycle. With tape-ins, iterations can be about a month or less, according to Part I (2015).
The distinction is between the time required to fabricate and evaluate a batch and the cadence at which a design team can prepare its next candidate. Tape-ins do not make fabrication take a month; they let teams have another design ready for the next cycle instead of waiting to begin a new iteration after the previous cycle ends.
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Combined with small scalable designs and faster FPGA feedback, this process limits how much a team must stake on any single late-stage build. It also gives a team multiple points at which to discover issues, rather than concentrating feedback near the end of a long project.
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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteWhy does the article treat reuse as a language problem?
Reusable hardware is not just a matter of copying blocks. Patterson and Nikolić argue that Verilog, VHDL, SystemVerilog, and SystemC do not offer the high-level reusable abstractions familiar from modern software languages. Their proposed direction is to express hardware construction at a higher level, so teams can parameterize designs and reuse generators instead of maintaining near-duplicate low-level descriptions.
What Chisel does in this approach
Chisel is presented as a hardware-construction language implemented in Scala. The article describes it as a way to generate RTL and target both FPGA EDIF and chip layout. The intended benefit is shared, parameterized design code: teams can use one generator approach across different RISC-V cores, adapting configurations without independently rewriting every implementation.
This is a design-method recommendation, not evidence that Chisel or any single language eliminates verification work. Generated implementations still need to be checked against their intended behavior, and the article does not provide a current comparison of languages, tools, or adoption.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How does software compatibility affect SoC cost?
A chip is useful only alongside software that can run on it. If different processors or product variants require incompatible instruction sets, teams may have to maintain separate software stacks. The article’s RISC-V example addresses that burden with a small open base instruction set that can run a common open-source software stack, while custom extensions can add application-specific functions.
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The authors present an open ISA as a way to share software across implementations and avoid instruction-set licensing fees. That does not mean all software, integration, or support costs disappear, nor does the 2015 article establish present-day RISC-V market share or the terms of every implementation. Its point is that software compatibility is a hardware-economics decision: preserving a common base can prevent each chip variant from becoming a separate software project.
What are the four cost-reduction guidelines?
- Make the die scalable. Keep the smallest manufacturable configuration useful, then scale it as requirements justify greater area and capability.
- Use agile verification and validation. Gather feedback from FPGA or silicon prototypes during development so functional, performance, energy, and integration questions are not all deferred to the final implementation.
- Reuse designs through modern-language abstractions. Use parameterized hardware construction, such as the article’s Chisel example, to share generators rather than duplicating low-level descriptions.
- Preserve software compatibility. Favor a common instruction-set and software foundation where possible, reserving custom extensions for needs that warrant them.
The recommendations address different sources of exposure: die area and manufacturing, late feedback, duplicated design work, and fragmented software. Patterson and Nikolić place typical SoC development cost at $30M–$100M in their 2015 discussion and say verification costs more than design. Those are historical estimates from the article, not a current budget benchmark.
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