Lauterbach and OpenSynergy announced on February 18, 2021, that TRACE32 had gained awareness of OpenSynergy’s COQOS hypervisor and the guest systems running on it. The release names COQOS ARM-A and ARM-R variants and highlights three debugging tasks: visualizing interrupts, debugging boot code from the first instruction, and inspecting guest operating system resources such as application code and process tables.
What TRACE32’s COQOS awareness does
The partnership announcement says the integration was intended to help engineers debug and trace complex systems on chip (SoCs) without needing detailed knowledge of how multiple operating systems interact. Its specific COQOS capabilities are:
- Visualize interrupts: inspect interrupt activity while debugging.
- Debug early boot: start debugging boot code from the first instruction.
- Inspect guest resources: examine guest OS resources, including application code and process tables.
These are the functions named in Lauterbach’s February 18, 2021 announcement. The release does not enumerate other COQOS-specific debugging functions.
Which COQOS variants are named?
The announcement explicitly identifies both the COQOS ARM-A and ARM-R variants. A Lauterbach hypervisor flyer also maps COQOS to Arm Cortex-A/Cortex-R (Armv8). That mapping is useful context, but neither reference provides a complete compatibility matrix or confirms fit for every processor, COQOS version, or TRACE32 configuration.
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For a specific target, confirm the processor and architecture, COQOS version and configuration, TRACE32 debug hardware and software, and the guest operating systems and OS-awareness support required. Also verify that each operation you need is available on that chip and product combination.
How to interpret the safety context
The 2021 release places COQOS in the context of consolidating functions on one ECU or MCU. It says COQOS provides freedom from interference for systems with different ASIL levels, up to ASIL-D. This describes the vendor announcement’s safety context; it is not evidence that a particular system or deployment is certified.
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How current TRACE32 hypervisor features relate
Lauterbach’s current Supported Hypervisors page describes hypervisor awareness generally: debugging and tracing across abstraction levels, viewing guest operating systems, switching between guests and processes, and debugging from user applications to device drivers.
Its OS- and Hypervisor-aware Debugging page also discusses concurrent OS-aware debugging for guest VMs, system-level views, task-aware breakpoints, and performance monitoring. These are general TRACE32 capabilities, not a COQOS-specific promise. Lauterbach states that individual feature availability depends on the chip and TRACE32 products; its technical overview likewise notes that supported solutions and features vary.
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What the announcement does not establish
- A complete list of supported processors, COQOS versions, or target configurations.
- That every general TRACE32 hypervisor feature is available with COQOS.
- Pricing, customer adoption, or measured debugging-efficiency results.
- Certification of a particular ECU, MCU, or safety deployment.
Lauterbach’s current Supported Architectures page cites support for more than 150 microprocessor architectures and more than 10,000 microprocessors. Those figures describe TRACE32’s overall vendor-published scope, not COQOS-specific coverage.
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